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101. 发明授权

US06667528B2 Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same 有权
标题翻译：具有反射镜和背面接触的绝缘体上半导体侧面p-i-n光电探测器及其形成方法
公开(公告)号：US06667528B2
公开(公告)日：2003-12-23
申请号：US10033902
申请日：2002-01-03
申请人： Guy Moshe Cohen , Kern Rim , Dennis L. Rogers , Jeremy Daniel Schaub , Min Yang
发明人： Guy Moshe Cohen , Kern Rim , Dennis L. Rogers , Jeremy Daniel Schaub , Min Yang
IPC分类号： H01L31058
CPC分类号： H01L31/105 , H01L31/03529 , H01L31/03921 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A photodetector (and method for producing the same) includes a semiconductor substrate, a buried insulator formed on the substrate, a buried mirror formed on the buried insulator, a semiconductor-on-insulator (SOI) layer formed on the conductor, alternating n-type and p-type doped fingers formed in the semiconductor-on-insulator layer, and a backside contact to one of the p-type doped fingers and the n-type doped fingers.
摘要翻译：光电检测器（及其制造方法）包括半导体衬底，形成在衬底上的埋入绝缘体，形成在埋层绝缘体上的掩埋反射镜，形成在导体上的绝缘体上半导体层（SOI）层，形成在绝缘体上半导体层中的p型和p型掺杂指，以及与p型掺杂指和n型掺杂指之一的背面接触。

102. 发明授权

US06429061B1 Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation 有权
标题翻译：在器件隔离形成之后使用Si的选择性外延沉积来制造应变Si CMOS结构的方法
公开(公告)号：US06429061B1
公开(公告)日：2002-08-06
申请号：US09626331
申请日：2000-07-26
申请人： Kern Rim
发明人： Kern Rim
IPC分类号： H01L21336
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/0245 , H01L21/02532 , H01L21/02639 , H01L21/823807 , H01L21/823878 , H01L29/66651 , Y10S438/933
摘要： A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe layer. These processing steps may be used in conjunction with conventional gate processing steps in forming a strained MOSFET structure.
摘要翻译：通过包括在衬底的表面上形成松弛的SiGe层的步骤形成应变Si CMOS结构; 在所述松弛SiGe层中形成隔离区和阱注入区; 并在所述松弛的SiGe层上形成应变Si层。这些处理步骤可以与形成应变MOSFET结构中的常规栅极处理步骤结合使用。

103. 发明授权

US07939413B2 Embedded stressor structure and process 有权
标题翻译：嵌入式应力器结构与过程
公开(公告)号：US07939413B2
公开(公告)日：2011-05-10
申请号：US11297522
申请日：2005-12-08
申请人： Yung Fu Chong , Zhijiong Luo , Joo Chan Kim , Brian Joseph Greene , Kern Rim
发明人： Yung Fu Chong , Zhijiong Luo , Joo Chan Kim , Brian Joseph Greene , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.
摘要翻译：示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫门。包括以下的示例性方法。我们在衬底的第一区域上提供栅极结构。栅极结构由栅极电介质，栅极和侧壁间隔物组成。我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。形成填充S / D凹槽的S / D应力区域。与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

104. 发明申请

US20110082680A1 COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS 失效
标题翻译：用于器件/电路/芯片泄漏电流（IDDQ）的紧凑型模型包括工艺引起的升级因素
公开(公告)号：US20110082680A1
公开(公告)日：2011-04-07
申请号：US12574440
申请日：2009-10-06
申请人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50 , G06F17/18 , G01R31/26
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

105. 发明授权

US07875511B2 CMOS structure including differential channel stressing layer compositions 有权
标题翻译： CMOS结构包括差分沟道应力层组成
公开(公告)号：US07875511B2
公开(公告)日：2011-01-25
申请号：US11685458
申请日：2007-03-13
申请人： Liu Yaocheng , Ricardo A. Donaton , Kern Rim
发明人： Liu Yaocheng , Ricardo A. Donaton , Kern Rim
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.
摘要翻译： CMOS结构包括包括n-FET沟道区的n-FET器件和包括p-FET沟道区的p-FET器件。 n-FET沟道区包括位于硅 - 锗合金材料层上的第一硅材料层。 p-FET沟道包括位于硅 - 锗 - 碳合金材料层上的第二硅材料层。硅 - 锗合金材料层在n-FET通道内引起所需的拉伸应变。硅 - 锗 - 合金材料层抑制了p-FET沟道区内的不希望的拉伸应变。可以通过选择性地将碳包含在形成硅 - 锗合金材料层的硅 - 锗合金材料中来形成由硅 - 锗 - 碳合金材料层构成的硅 - 锗 - 碳合金材料。

106. 发明授权

US07808081B2 Strained-silicon CMOS device and method 有权
标题翻译：应变硅CMOS器件及方法
公开(公告)号：US07808081B2
公开(公告)日：2010-10-05
申请号：US11619511
申请日：2007-01-03
申请人： Andres Bryant , Qiqing Ouyang , Kern Rim
发明人： Andres Bryant , Qiqing Ouyang , Kern Rim
IPC分类号： H01L29/06
CPC分类号： H01L21/823807 , H01L21/7624 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/7849
摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.
摘要翻译：本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。本发明还提供了用应变诱导隔离区增加双轴应变的方法。本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

107. 发明授权

US07737032B2 MOSFET structure with multiple self-aligned silicide contacts 有权
标题翻译：具有多个自对准硅化物触点的MOSFET结构
公开(公告)号：US07737032B2
公开(公告)日：2010-06-15
申请号：US12131973
申请日：2008-06-03
申请人： Kevin K. Chan , Christian Lavoie , Kern Rim
发明人： Kevin K. Chan , Christian Lavoie , Kern Rim
IPC分类号： H01L21/44
CPC分类号： H01L29/66507 , H01L29/6653 , H01L29/7833
摘要： A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.
摘要翻译：提供了包括多个不同的自对准硅化物触点的金属氧化物半导体场效应晶体管（MOSFET）结构及其制造方法。 MOSFET结构包括至少一个金属氧化物半导体场效应晶体管，其具有包括位于含Si衬底的表面上的栅极边缘的栅极导体; 第一内部硅化物，其具有基本上与所述至少一个金属氧化物半导体场效应晶体管的栅极边缘对准的边缘; 以及位于第一内部硅化物附近的第二外部硅化物。根据本发明，第二外部硅化物的第二厚度大于第一内部硅化物的第一厚度。此外，第二外部硅化物的电阻率低于第一内部硅化物的电阻率。

108. 发明授权

US07675055B2 Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof 失效
标题翻译：旋转晶片上的应变互补金属氧化物半导体（CMOS）及其方法
公开(公告)号：US07675055B2
公开(公告)日：2010-03-09
申请号：US11925088
申请日：2007-10-26
申请人： Meikei Ieong , Qiging C. Ouyang , Kern Rim
发明人： Meikei Ieong , Qiging C. Ouyang , Kern Rim
IPC分类号： H01L31/00
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
摘要翻译：本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变，一个紧张的班轮。本发明还提供了制造上述半导体结构的方法。

109. 发明申请

US20090305474A1 STRAINED-SILICON CMOS DEVICE AND METHOD 审中-公开
标题翻译：应变硅CMOS器件及方法
公开(公告)号：US20090305474A1
公开(公告)日：2009-12-10
申请号：US12540862
申请日：2009-08-13
申请人： Andres Bryant , Qiqing Ouyang , Kern Rim
发明人： Andres Bryant , Qiqing Ouyang , Kern Rim
IPC分类号： H01L21/31 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/7624 , H01L21/823814 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/7849
摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.
摘要翻译：本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。本发明还提供了用应变诱导隔离区增加双轴应变的方法。本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

110. 发明授权

US07507989B2 Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 有权
公开(公告)号：US07507989B2
公开(公告)日：2009-03-24
申请号：US11927006
申请日：2007-10-29
申请人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
发明人： Kevin K. Chan , Jack O. Chu , Kern Rim , Leathen Shi
IPC分类号： H01L29/06
CPC分类号： H01L29/78687 , H01L21/2007 , H01L29/1054 , H01L29/517 , H01L29/66742 , H01L29/7833 , H01L29/7842 , H01L29/78603
摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

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