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101. 发明授权

US5878485A Method for fabricating a carrier for testing unpackaged semiconductor dice 失效
标题翻译：制造用于测试未封装的半导体晶片的载体的方法
公开(公告)号：US5878485A
公开(公告)日：1999-03-09
申请号：US615119
申请日：1996-03-13
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , H01R43/00
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/75 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R3/00 , G01R31/2863 , H01L2224/05553 , H01L2224/16145 , H01L2224/48 , H01L2224/75 , H01L2224/85001 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423 , Y10T29/49117 , Y10T29/49155 , Y10T29/49158 , Y10T29/49172
摘要： A method for fabricating a carrier for testing an unpackaged semiconductor die is provided. The carrier includes a carrier base for supporting the die; an interconnect for establishing a temporary electrical connection with the die; and a force distribution mechanism for biasing the die and interconnect together. In an illustrative embodiment the carrier is formed with a laminated ceramic base. The ceramic base includes internal conductive lines that are wire bonded to the interconnect and metal plated external contacts that are connected to external test circuitry. In an alternate embodiment the carrier is formed with an injection molded plastic base and includes 3-D circuitry formed by a metallization and photolithographic process. In either case, the carrier is adapted for testing different die configurations by interchanging different interconnects.
摘要翻译：提供了一种用于制造用于测试未封装的半导体管芯的载体的方法。载体包括用于支撑模具的载体基体; 用于建立与所述管芯的临时电连接的互连; 以及用于偏压模具并互连在一起的力分配机构。在说明性实施例中，载体形成有层压陶瓷基底。陶瓷基座包括内部导电线，引线连接到互连线和金属电镀外部触点，连接到外部测试电路。在替代实施例中，载体由注射成型的塑料基底形成，并且包括通过金属化和光刻工艺形成的3-D电路。在任一情况下，载体适于通过互换不同的互连来测试不同的管芯配置。

102. 发明授权

US5408190A Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die 失效
标题翻译：具有用于非封装模具的离散模具老化的衬底互连的测试装置
公开(公告)号：US5408190A
公开(公告)日：1995-04-18
申请号：US073005
申请日：1993-06-07
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R1/04 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： H05K3/4007 , G01R1/0466 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/85 , G01R1/0483 , G01R3/00 , G01R31/2863 , H01L2224/05554 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/15787 , H01L2924/16195 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A reusable burn-in/test fixture for discrete die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. Electrical contact with bondpads or bumps on the die is established through an intermediate substrate. When the two halves are assembled, electrical contact with the die is established. The fixture establishes the electrical contact and with a burn-in oven and with a discrete die tester. The test fixture need not be opened until the burn-in and electrical tests are completed. The fixture permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. The intermediate substrate may be formed of semiconductor material or of a ceramic insulator. A Z-axis anisotropic conductive interconnect material may be interposed between the intermediate substrate and the die.
摘要翻译：用于离散模具的可重复使用的老化/测试夹具由两半组成。测试夹具的前半部分包含插入模具的腔体。通过中间基板建立与管芯上的焊盘或凸块的电接触。当组装两个半部时，建立与模具的电接触。固定装置建立了电气接触，并配有一个老化烘箱和一个独立的模具测试仪。在老化和电气测试完成之前，测试夹具不需要打开。夹具允许在组装之前对模具进行表征，使得模具然后可以以未包装的形式传送。中间基板可以由半导体材料或陶瓷绝缘体形成。 Z轴各向异性导电互连材料可以介于中间基板和模具之间。

103. 发明申请

US20080138973A1 MICROELECTRONIC DEVICES AND METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC DEVICES 有权
标题翻译：用于在微电子设备中形成互连的微电子器件和方法
公开(公告)号：US20080138973A1
公开(公告)日：2008-06-12
申请号：US12027106
申请日：2008-02-06
申请人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , David R. Hembree , Sidney B. Rigg , Warren M. Farnworth , William M. Hiatt
IPC分类号： H01L21/44 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L2224/48091 , H01L2224/48465 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H05K1/0306 , H05K3/4038 , H05K3/422 , H05K3/423 , H05K2201/0305 , H05K2201/09827 , H05K2203/072 , H05K2203/1147 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material.
摘要翻译：本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微电子器件中形成互连的方法。在一个实施例中，一种方法包括提供具有正面和背面的微电子衬底。衬底具有包括集成电路的微电子管芯和可操作地耦合到集成电路的端子。该方法还包括至少部分地形成通过基底并且在基底的前侧和/或后侧具有开口的通道。该方法还包括用封闭通道一端的导电盖密封开口，同时通道的另一端保持打开。该方法然后包括用导电材料填充通道。

104. 发明授权

US06628128B1 CSP BGA test socket with insert and method 失效
公开(公告)号：US06628128B1
公开(公告)日：2003-09-30
申请号：US09651860
申请日：2000-08-30
申请人： Warren M. Farnworth , Derek J. Gochnour , David R. Hembree
发明人： Warren M. Farnworth , Derek J. Gochnour , David R. Hembree
IPC分类号： G01R3102
CPC分类号： H05K1/112 , G01R1/0483 , H05K3/325 , H05K2201/09472 , H05K2201/09827 , H05K2201/10734
摘要： A BGA test socket for use in standard testing and burn-in testing of BGA dies and method for testing such dies is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dies can be reliably tested including chip scale packaged (“CSP”) BGA dies. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dies and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dies through closing the test socket before removing the die deposit probe.

105. 发明授权

US06358833B1 Method of fabricating a micromachined chip scale package 失效
标题翻译：制造微加工芯片级封装的方法
公开(公告)号：US06358833B1
公开(公告)日：2002-03-19
申请号：US09651601
申请日：2000-08-30
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth
IPC分类号： H01L2144
CPC分类号： H01L23/13 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05147 , H01L2224/05171 , H01L2224/05647 , H01L2224/1148 , H01L2224/13099 , H01L2224/131 , H01L2224/1319 , H01L2224/13339 , H01L2224/16237 , H01L2924/0001 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2224/29099 , H01L2924/00014 , H01L2924/0665 , H01L2924/00 , H01L2924/013
摘要： A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.
摘要翻译：芯片级封装由半导体管芯组成，半导体管芯具有层压在其有源表面上的硅片。模具的接合焊盘通过微机械加工通过坯件的孔进入。该封装可以与引线接合使用，或者可以将焊料或其它导电凸块放置在用于倒装芯片应用的空白孔中。此外，可以使用封装将管芯的外部连接重新路由到其他位置，例如集中式球栅阵列或用于直接或离散管芯连接（DDC）到载体的边缘连接装置。优选的是，芯片级封装形成在晶片级，作为如此形成的多个封装之一，其形成有晶片级坯料，并且整个晶片被烧入并测试以识别已知的良好裸片（KGD ），然后将晶片层压板分离成单个包装。

106. 发明授权

US06285203B1 Test system having alignment member for aligning semiconductor components 有权
公开(公告)号：US06285203B1
公开(公告)日：2001-09-04
申请号：US09332838
申请日：1999-06-14
申请人： Salman Akram , Warren M. Farnworth , Michael E. Hess , David R. Hembree
发明人： Salman Akram , Warren M. Farnworth , Michael E. Hess , David R. Hembree
IPC分类号： G01R102
CPC分类号： G01R1/0483 , G01R31/2886 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/8592 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/10157 , H01L2924/10253 , H01L2924/15312 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A test system for testing semiconductor components includes an interconnect having contacts for making temporary electrical connections with terminal contacts on the components. The interconnect contacts can be configured to electrically engage planar terminal contacts (e.g., bond pads, test pads) or bumped terminal contacts (e.g., solder bumps, solder balls) on the components. The test system also includes an alignment member for aligning the components to the interconnect. Different embodiments of the alignment member include: a curable polymer material molded in place on the interconnect; an alignment opening formed as an etched pocket in a substrate of the interconnect; and a separate fence attached to the interconnect using an alignment fixture.

107. 发明授权

US6025728A Semiconductor package with wire bond protective member 失效
标题翻译：半导体封装带引线键合保护元件
公开(公告)号：US6025728A
公开(公告)日：2000-02-15
申请号：US845782
申请日：1997-04-25
申请人： David R. Hembree , Salman Akram , Derek Gochnour , Warren M. Farnworth
发明人： David R. Hembree , Salman Akram , Derek Gochnour , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R31/02
CPC分类号： G01R1/0483 , H01L2224/48091 , H01L2924/01079 , H01L2924/16195
摘要： A package, system and method for testing semiconductor dice are provided. The package include a base for retaining the die, and an interconnect having contact members for establishing temporary electrical connections with the die. Electrical paths are formed between terminal contacts on the base, and the contact members on the interconnect, by wires that are wire bonded to conductors on the base and interconnect. The package includes a protective member for protecting the wires and associated wire bonds during assembly, disassembly and handling of the package. The protective member can be formed as a plate mounted to the base and configured to cover the wires and wire bonds. Alternately the protective member can comprise an encapsulating material such as an epoxy resin or silicone elastomer deposited on the wires and wire bonds and then cured.
摘要翻译：提供了一种用于测试半导体晶片的封装，系统和方法。该封装包括用于保持裸片的基座和具有与模具建立临时电连接的接触构件的互连。通过引线接合到基座上的导体和互连件上的导线，在基座上的端子触头与互连件上的接触部件之间形成电气路径。该包装包括用于在组装，拆卸和处理包装过程中保护电线和相关联的线接合的保护构件。保护构件可以形成为安装到基座并被构造成覆盖电线和引线接合的板。替代地，保护构件可以包括诸如环氧树脂或硅氧烷弹性体的封装材料，其沉积在电线和引线键上，然后固化。

108. 发明授权

US5893726A Semiconductor package with pre-fabricated cover and method of fabrication 失效
标题翻译：具有预制盖的半导体封装和制造方法
公开(公告)号：US5893726A
公开(公告)日：1999-04-13
申请号：US990866
申请日：1997-12-15
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
IPC分类号： H01L23/04 , H01L23/10 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/10 , H01L23/04 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195
摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.
摘要翻译：半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。盖可以用模制塑料或冲压金属预制，并使用固化的密封件附接到基底。还可以通过基底提供孔，以在形成密封期间允许压力平衡。盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

109. 发明授权

US5726075A Method for fabricating microbump interconnect for bare semiconductor dice 失效
标题翻译：用于制造裸半导体晶片的微型块互连的方法
公开(公告)号：US5726075A
公开(公告)日：1998-03-10
申请号：US624991
申请日：1996-03-29
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour
IPC分类号： H01L21/48 , H01L21/60 , H01L21/28
CPC分类号： H01L24/11 , H01L21/4853 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042
摘要： A method for forming an interconnect for a bare semiconductor is provided. The interconnect includes an insulating film with a pattern of conductors and microbumps adapted to make an electrical connection with contact locations on the die. The insulating film and conductors are mounted to a rigid substrate (e.g., silicon) using an lo elastomeric adhesive. The method includes forming conductive bus bars in electrical communication with the pattern of conductors to provide an electrical path for electroplating the microbumps onto the conductors. Following the electroplating step, the bus bars are severed and separate electrical paths are formed to the conductors. The bus bar can also be used in the completed interconnect to provide a common electrical path to select conductors. The interconnect can be used for testing the die or for providing a permanent electrical connection to the die.
摘要翻译：提供了一种用于形成裸半导体的互连的方法。互连包括绝缘膜，其具有适于与裸片上的接触位置进行电连接的导体和微胶片图案。绝缘膜和导体使用弹性体粘合剂安装到刚性基底（例如硅）上。该方法包括形成与导体图案电连通的导电母线，以提供用于将微胶片电镀到导体上的电路径。在电镀步骤之后，母线被切断，并且与导体形成分开的电路径。母线也可用于完成的互连，以提供选择导体的公共电路。互连可用于测试管芯或提供与管芯的永久电连接。

110. 发明申请

US20110111561A1 INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS, AND ASSOCIATED SYSTEMS AND METHODS 有权
标题翻译：用于堆叠式DIES的互连结构，包括通过硅素的渗透结构以及相关系统和方法
公开(公告)号：US20110111561A1
公开(公告)日：2011-05-12
申请号：US13007002
申请日：2011-01-14
申请人： Owen R. Fay , Warren M. Farnworth , David R. Hembree
发明人： Owen R. Fay , Warren M. Farnworth , David R. Hembree
IPC分类号： H01L21/607
CPC分类号： H01L23/5384 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/03444 , H01L2224/0346 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05011 , H01L2224/05012 , H01L2224/05017 , H01L2224/05025 , H01L2224/05027 , H01L2224/05144 , H01L2224/05147 , H01L2224/05551 , H01L2224/05558 , H01L2224/05562 , H01L2224/05611 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/11474 , H01L2224/1161 , H01L2224/1162 , H01L2224/1182 , H01L2224/11823 , H01L2224/11825 , H01L2224/11826 , H01L2224/11831 , H01L2224/11903 , H01L2224/13017 , H01L2224/13018 , H01L2224/13019 , H01L2224/13075 , H01L2224/13082 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13562 , H01L2224/13611 , H01L2224/13644 , H01L2224/13687 , H01L2224/16145 , H01L2224/16146 , H01L2224/16147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/29011 , H01L2224/2919 , H01L2224/48091 , H01L2224/48227 , H01L2224/73103 , H01L2224/73203 , H01L2224/73257 , H01L2224/81139 , H01L2224/81191 , H01L2224/81205 , H01L2224/81345 , H01L2224/81365 , H01L2224/81815 , H01L2224/81898 , H01L2224/831 , H01L2224/83141 , H01L2224/83193 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/11 , H01L2224/03 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要： Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
摘要翻译：公开了用于堆叠管芯的互连结构，包括贯穿硅通孔的穿透结构以及相关的系统和方法。根据特定实施例的系统包括具有第一衬底材料的第一半导体衬底和由第一半导体衬底承载的穿透结构。该系统还包括第二半导体衬底，该第二半导体衬底具有带有预制凹槽的第二衬底材料。第一半导体衬底的穿透结构被容纳在第二半导体衬底的凹部中，并且与凹部机械地接合并固定到第二半导体衬底。

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