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101. 再颁专利

USRE41021E1 Multi-state EEPROM having write-verify control circuit 有权
公开(公告)号：USRE41021E1
公开(公告)日：2009-12-01
申请号：US11451588
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/34
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

102. 再颁专利

USRE41019E1 Multi-state EEPROM having write-verify control circuit 有权
公开(公告)号：USRE41019E1
公开(公告)日：2009-12-01
申请号：US11451589
申请日：2006-06-13
申请人： Tomoharu Tanaka , Gertjan Hemink
发明人： Tomoharu Tanaka , Gertjan Hemink
IPC分类号： G11C16/26
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642
摘要： An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory cells, a write circuit for performing a write operation in accordance with the contents of the data circuits respectively corresponding to the memory cells, a write verify circuit for confirming states of the memory cells set upon the write operation, and a data updating circuit for updating the contents of the data circuits such that a rewrite operation is performed to only a memory cell, in which data is not sufficiently written, on the basis of the contents of the data circuits and the states of the memory cells set upon the write operation. A write operation, a write verify operation, and a data circuit content updating operation based on the contents of the data circuits are repeatedly performed until the memory cells are set in predetermined written states.

103. 发明申请

US20090180333A1 Semiconductor memory column decoder device and method 有权
标题翻译：半导体存储器列解码器装置及方法
公开(公告)号：US20090180333A1
公开(公告)日：2009-07-16
申请号：US12008417
申请日：2008-01-10
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
摘要翻译：半导体存储器件和方法包括在阱中制造的闪存单元阵列，同一列中的存储单元彼此串联连接并连接到相应的位线。存储器件还包括列解码器，数据寄存器缓冲器单元，行解码器，擦除控制单元和输入/输出缓冲器单元。在一个或多个实施例中，擦除控制单元以避免由在井中制造的晶体管形成的p-n结分解的方式向阱施加电压以擦除存储器单元。在另一个实施例中，高压晶体管用于选择性地将位线隔离并将位线成对地耦合到外围电路，使得每个高压晶体管由两个位线共享。

104. 发明授权

US07468908B2 Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell 有权
标题翻译：适用于将多值存储在单个存储单元中的非易失性半导体存储器件
公开(公告)号：US07468908B2
公开(公告)日：2008-12-23
申请号：US11929152
申请日：2007-10-30
申请人： Tomoharu Tanaka
发明人： Tomoharu Tanaka
IPC分类号： G11C11/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454
摘要： A non-volatile semiconductor memory device includes a non-volatile memory cell and a write circuit that is adapted to write data to the memory cell by supplying a write voltage and a write control voltage to the memory cell to change the write state of the memory cell, changing the supply of the write control voltage to reduce the rate of changing the write state, further changing the supply of the write control voltage to control the reduced rate of changing the write state and terminating the write operation to the memory cell while the rate of changing the write state is reduced.
摘要翻译：非易失性半导体存储器件包括非易失性存储器单元和写入电路，其适于通过向存储器单元提供写入电压和写入控制电压来将数据写入存储器单元，以改变存储器的写入状态单元，改变写入控制电压的供应以减小改变写入状态的速率，进一步改变写入控制电压的供应以控制改变写入状态的降低速率并且终止对存储器单元的写入操作，同时降低写入状态的速率。

105. 发明授权

US07394695B2 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
标题翻译：具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
公开(公告)号：US07394695B2
公开(公告)日：2008-07-01
申请号：US11511488
申请日：2006-08-29
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
摘要翻译：具有三个以上值的数据以非易失性方式存储在存储单元中。数据电路具有多个存储电路。多个存储电路中的一个是锁存电路。多个存储电路中的另一个是电容器。锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。结果，即使使用多级数据，数据电路也不会变大。

106. 发明授权

US07164605B2 Semiconductor memory device and electric device with the same 有权
标题翻译：半导体存储器件和电器件相同
公开(公告)号：US07164605B2
公开(公告)日：2007-01-16
申请号：US11305193
申请日：2005-12-19
申请人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
发明人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/06
CPC分类号： G11C16/3468
摘要： A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.
摘要翻译：半导体存储器件包括：多个单元阵列块，每个单元阵列块中布置有多个存储单元; 用于选择单元阵列块中的存储单元的地址解码电路; 用于读取单元阵列块的单元数据的读出放大器电路; 以及用于向芯片外部产生忙信号的忙信号产生电路，其中在第一读周期中选择第一单元阵列块中的第一区，对第一单元阵列块的第一区进行单元数据读操作，同时执行第二单元阵列块的区域，而忙信号产生电路产生真正的忙信号，然后执行读数据输出操作，以将保持在读出放大器电路中的第一区域的读出数据输出到芯片外部，并且在第二读取周期中选择第二单元阵列块中的第二区域，在忙信号产生电路在不执行单元数据读取操作的情况下输出比真实忙信号更短的时间长度的虚拟忙信号，读取执行数据输出操作，以将保持在读出放大器电路中的第二区域的读出数据输出到芯片外部。

107. 发明授权

US07120052B2 Semiconductor memory device for storing multivalued data 有权
公开(公告)号：US07120052B2
公开(公告)日：2006-10-10
申请号：US11325917
申请日：2006-01-04
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.

108. 发明授权

US07106627B2 Nonvolatile semiconductor memory device with redundancy and security information circuitry 有权
标题翻译：具有冗余和安全信息电路的非易失性半导体存储器件
公开(公告)号：US07106627B2
公开(公告)日：2006-09-12
申请号：US11194716
申请日：2005-08-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/22 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has memory elements selected by an address signal. The second storage area has memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区域具有由地址信号选择的存储元件。第二存储区域具有通过控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

109. 发明授权

US07046555B2 Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance 有权
标题翻译：用于识别具有差的亚阈值斜率或弱跨导的非易失性存储元件的方法
公开(公告)号：US07046555B2
公开(公告)日：2006-05-16
申请号：US10665685
申请日：2003-09-17
申请人： Jeffrey W. Lutze , Jian Chen , Yan Li , Kazunori Kanebako , Tomoharu Tanaka
发明人： Jeffrey W. Lutze , Jian Chen , Yan Li , Kazunori Kanebako , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C16/3495 , G11C16/04 , G11C16/349 , G11C29/50 , G11C29/50004
摘要： A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.
摘要翻译：用于鉴定具有差的亚阈值斜率和降低的跨导的细胞的许多方法。第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然进行。第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。偏移量可以用来区分好的元素和坏的元素。

110. 发明申请

US20050265092A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050265092A1
公开(公告)日：2005-12-01
申请号：US11194716
申请日：2005-08-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G06F12/16 , G11C7/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/06 , G11C29/42
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

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