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101. 发明授权

US09217773B2 Addressable tap selection aux i/o, linking, address, instruction, control circuitry 有权
标题翻译：可寻址抽头选择辅助i / o，链接，地址，指令，控制电路
公开(公告)号：US09217773B2
公开(公告)日：2015-12-22
申请号：US14567299
申请日：2014-12-11
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31722 , G01R31/31723 , G01R31/31727 , G01R31/318541 , G01R31/318558
摘要： This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
摘要翻译：本公开描述了可以在集成电路中的集成电路或嵌入式核心上使用的减少的引脚总线。总线可用于串行访问电路，其中IC或引脚上的引脚的可用性受限制。总线可用于各种串行通信操作，例如但不限于IC或核心设计的串行通信相关测试，仿真，调试和/或跟踪操作。本公开的其他方面包括使用减少的针脚总线用于仿真，调试和跟踪操作以及功能操作。在本公开的第五方面中，一种接口选择电路，图41-49提供了选择性地使用图5的5信号接口。 41或图3的3信号接口。 8。

102. 发明申请

US20150355987A1 AT-SPEED TEST ACCESS PORT OPERATIONS 审中-公开
公开(公告)号：US20150355987A1
公开(公告)日：2015-12-10
申请号：US14830244
申请日：2015-08-19
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G06F11/26
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318555 , G01R31/318572 , G06F11/26 , H01L27/1222 , H01L27/1225 , H01L27/1248 , H01L27/3246 , H01L27/3248 , H01L27/3258 , H01L27/3262 , H01L51/5212 , H01L51/5215 , H01L51/5253 , H01L51/56 , H01L2227/323 , H01L2251/301 , H01L2251/308
摘要： This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.

103. 发明申请

US20150338459A1 SCAN RESPONSE REUSE METHOD AND APPARATUS 审中-公开
标题翻译：扫描响应重用方法和设备
公开(公告)号：US20150338459A1
公开(公告)日：2015-11-26
申请号：US14735806
申请日：2015-06-10
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31724 , G01R31/31725 , G01R31/318536 , G01R31/318544
摘要： The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.
摘要翻译：本公开描述了一种用于允许从被测电路的扫描输出输出的响应数据被格式化并作为输入到被测电路的扫描输入的刺激数据的新的方法和装置。此外，本公开描述了一种用于允许从被测电路的扫描输出输出的响应数据被格式化并用作预期数据以与从被测电路输出的响应数据进行比较的新颖方法和装置。在本公开中还提供和描述了另外的实施例。

104. 发明申请

US20150316612A1 GATING TAP REGISTER CONTROL BUS AND AUXILIARY/WRAPPER TEST BUS 审中-公开
公开(公告)号：US20150316612A1
公开(公告)日：2015-11-05
申请号：US14800276
申请日：2015-07-15
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/31723 , G01R31/31724 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318508 , G01R31/318536 , G06F17/5081
摘要： In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.

105. 发明申请

US20150309116A1 ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION 审中-公开
公开(公告)号：US20150309116A1
公开(公告)日：2015-10-29
申请号：US14792398
申请日：2015-07-06
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/31721 , G01R31/31723 , G01R31/31724 , G01R31/3177 , G01R31/318536 , G01R31/318575
摘要： A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

106. 发明申请

US20150285861A1 SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS 审中-公开
公开(公告)号：US20150285861A1
公开(公告)日：2015-10-08
申请号：US14744767
申请日：2015-06-19
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G01R31/318536 , G01R31/318572 , G01R31/318577
摘要： Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

107. 发明授权

US09134376B2 TDO multiplexers series coupling augmentation instruction register with instruction registers 有权
标题翻译： TDO多路复用器串联扩充指令寄存器与指令寄存器
公开(公告)号：US09134376B2
公开(公告)日：2015-09-15
申请号：US14605329
申请日：2015-01-26
申请人： Texas Instruments Incorporated
发明人： Baher S. Haroun , Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3177
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G11C29/46
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译：描述了用于在集成电路上测试多个电路的架构。该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

108. 发明授权

US09128152B2 Interface circuitry with JTAG interface, full and reduced pin interfaces 有权
标题翻译：接口电路，具有JTAG接口，全引脚和降低引脚接口
公开(公告)号：US09128152B2
公开(公告)日：2015-09-08
申请号：US14456125
申请日：2014-08-11
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/302 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/31713 , G01R31/2815 , G01R31/2851 , G01R31/2884 , G01R31/3025 , G01R31/31703 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318558
摘要： The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
摘要翻译：本公开描述了用于访问基板上的设备的过程和设备。衬底可以仅包括全引脚JTAG器件（504），只有减少的引脚JTAG器件（506），或者是完全引脚和降低引脚JTAG器件的混合。使用在基板（408）和JTAG控制器（404）之间的单个接口（502）来实现访问。访问接口可以是有线接口或无线接口，并且可以用于基于JTAG的设备测试，调试，编程或其他类型的基于JTAG的操作。

109. 发明申请

US20150247897A1 ADDRESSABLE TEST ACCESS PORT METHOD AND APPARATUS 有权
公开(公告)号：US20150247897A1
公开(公告)日：2015-09-03
申请号：US14698298
申请日：2015-04-28
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318555 , G01R31/318572
摘要： The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

110. 发明授权

US09121903B2 Parallel scan path distributor/collector controller having serial and control inputs 有权
标题翻译：具有串行和控制输入的并行扫描路径分配器/收集器控制器
公开(公告)号：US09121903B2
公开(公告)日：2015-09-01
申请号：US14547781
申请日：2014-11-19
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318544 , G01R31/31855 , G01R31/318555 , G01R31/318575
摘要： Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.
摘要翻译：功能电路和电路核心使用扫描路径在集成电路上进行测试。为这些扫描路径使用并行扫描分配器和集电极电路可以改善IC内部电路和内核的测试访问，并降低了扫描测试期间的IC功耗。用于分配器和集电极电路的控制器包括测试控制寄存器，测试控制状态机和多路复用器。这些测试电路可以以层次结构或并行连接。传统的测试访问端口或TAP可以被修改为与公开的测试电路一起工作。

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