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101. 发明授权

US06629191B1 Nonvolatile memory apparatus for storing data from a host 有权
标题翻译：用于存储来自主机的数据的非易失性存储装置
公开(公告)号：US06629191B1
公开(公告)日：2003-09-30
申请号：US09340140
申请日：1999-06-28
申请人： Kunihiro Katayama , Takayuki Tamura , Kazuo Nakamura
发明人： Kunihiro Katayama , Takayuki Tamura , Kazuo Nakamura
IPC分类号： G06F1206
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： In a memory including a flash memory, the life of the memory is prevented from being decreased due to the high frequency of rewrite operations of data to a specific area. When the erasure frequency of a block 301, storing four sectors of data, is high, each sector of block 301 is transferred to different blocks 302-305 to avoid deterioration of the data of block 301 due to the high frequency of rewriting.
摘要翻译：在包括闪速存储器的存储器中，由于将数据重写到特定区域的高频率，防止存储器的寿命减少。当存储四个数据扇区的块301的擦除频率高时，块301的每个扇区被传送到不同的块302-305，以避免由于重写的高频而导致块301的数据的劣化。

102. 发明授权

US06557088B2 Information processing system and recording medium recording a program to cause a computer to execute steps 失效
标题翻译：记录程序的信息处理系统和记录介质，使计算机执行步骤
公开(公告)号：US06557088B2
公开(公告)日：2003-04-29
申请号：US10196184
申请日：2002-07-17
申请人： Takayuki Tamura
发明人： Takayuki Tamura
IPC分类号： G06F1318
CPC分类号： G06F3/0607 , G06F3/0613 , G06F3/064 , G06F3/0656 , G06F3/0659 , G06F3/0674
摘要： An information processing system which has a disk buffer for temporarily storing data items read from a disk unit, a block processing order determination module for detecting, from a processing request for requesting data items stored on the disk unit, a data item matching the data stored in the disk buffer from the data items requested in the processing request and determining the read order of the data item matching and the remaining data requested in the processing request so that the data item matching is read before the remaining data, and a read module for reading the data item matching from the disk buffer before reading the remaining data into the disk buffer from the disk unit in accordance with the read order determined by the block processing order determination module.
摘要翻译：一种信息处理系统，具有用于临时存储从盘单元读取的数据项的盘缓冲器，块处理顺序确定模块，用于从存储在盘单元上的请求数据项的处理请求检测与存储的数据匹配的数据项在来自处理请求中请求的数据项的磁盘缓冲器中，并确定数据项匹配的读取顺序和处理请求中请求的剩余数据，使得在剩余数据之前读取数据项匹配，以及读取模块在根据由块处理顺序确定模块确定的读取顺序从磁盘单元读取剩余数据到磁盘缓冲器之前，读取与磁盘缓冲器匹配的数据项。

103. 发明授权

US06535422B2 Nonvolatile memory system 有权
公开(公告)号：US06535422B2
公开(公告)日：2003-03-18
申请号：US10023882
申请日：2001-12-21
申请人： Hiroyuki Goto , Shigemasa Shiota , Takayuki Tamura , Hirofumi Shibuya , Yasuhiro Nakamura
发明人： Hiroyuki Goto , Shigemasa Shiota , Takayuki Tamura , Hirofumi Shibuya , Yasuhiro Nakamura
IPC分类号： G11C1604
CPC分类号： G11C8/12 , G11C16/08 , G11C16/20
摘要： The present invention provides a nonvolatile memory system whose storage capacity can be easily changed. The nonvolatile memory system comprises plural memory modules, a controller for controlling the operation of the plural memory modules according to access requests from the outside, and a module selecting decoder for selectively enabling the memory modules by decoding a selection signal outputted from the controller, wherein the memory modules are freely mounted or dismounted. With this arrangement, the storage capacity can be changed by increasing or decreasing the memory modules.

104. 发明授权

US06285595B1 Semiconductor memory having electrically erasable and programmable nonvolatile semiconductor memory cells 有权
标题翻译：具有电可擦除和可编程的非易失性半导体存储单元的半导体存储器
公开(公告)号：US06285595B1
公开(公告)日：2001-09-04
申请号：US09537722
申请日：2000-03-30
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell. As a result of these operations, the semiconductor memory can determine the pieces of bit data in the order of the buffer A and the buffer B every time the discriminating operation is performed with respect to the cell.
摘要翻译：半导体存储器包括由多个单元组成的存储块，写入控制部分和读取控制部分。写入控制部分以这样一种方式设置多个单元中的每一个的电位，使得该电位对应于通过布置存储在缓冲器A和B中的位数据获得的位数据串所指示的电平，以缓冲器A和缓冲器B的顺序存储在单元中。读取控制部分具有与多个单元中的每一个对应的鉴别器。鉴别器将阈值电压设置为对应于相对于相应小区执行的识别操作的数量的电位电平和相对于该单元执行的鉴别操作的结果。作为这些操作的结果，半导体存储器可以在每次对单元执行鉴别操作时，以缓冲器A和缓冲器B的顺序来确定位数据。

105. 发明授权

US06199187B1 External storage device and memory access control method thereof 有权
公开(公告)号：US06199187B1
公开(公告)日：2001-03-06
申请号：US09544609
申请日：2000-04-06
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： H03M1300
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N−1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N−th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N−1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N−th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N−th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e., simultaneously), error detection and error correction of the (2N+1)th sector data (next sector data to be read by the host computer) read out from one of the first computer and second computer can be performed in the error correcting means. Consequently, the host computer always reads sector data, and at the same time, error detection and the error correction for a next sector data are simultaneously performed thereby the time required for error detection and error correction can be reduced apparently (i.e., made transparent to the host computer 2) and memory access can be obtained.

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