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101. 发明申请

US20070170513A1 Semiconductor Device and Manufacturing Method Thereof 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070170513A1
公开(公告)日：2007-07-26
申请号：US11694467
申请日：2007-03-30
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

102. 发明授权

US07157321B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07157321B2
公开(公告)日：2007-01-02
申请号：US10963822
申请日：2004-10-14
申请人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
发明人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
IPC分类号： H01L21/338 , H01L21/84
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1259 , H01L29/6675 , H01L29/78621 , H01L29/78648
摘要： A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: forming a semiconductor layer 3 having a source and a drain regions 10, 11, and LDD regions 16, 17; a gate insulating film 5; and a gate electrode 6; forming a first and a second interlayer insulating films 24, 25 over the gate electrode 6 and the gate insulating film 5; forming contact holes 25a, 25c to these interlayer insulating films so as to be located over each of the source region and the drain region; and an opening portion 25b to these interlayer insulating films so as to be located over the gate electrode and the LDD region; forming a second gate electrode 26b by a conductive film in the opening portion so as to cover the gate electrode and the LDD region; and a pixel electrode 26a over the second interlayer insulating film; removing the gate insulating film in the contact hole; and forming wirings 27, 28 connected to each the source region and the drain region.
摘要翻译：公开了可以通过减少掩模数而降低成本的半导体器件，并且公开了一种用于制造半导体器件的方法。制造半导体器件的方法包括以下步骤：形成具有源极和漏极区域10,11以及LDD区域16,17的半导体层3; 栅极绝缘膜5; 和栅电极6; 在栅极电极6和栅极绝缘膜5上形成第一和第二层间绝缘膜24,25; 向这些层间绝缘膜形成接触孔25a，25c，以便位于源极区域和漏极区域之上; 和这些层间绝缘膜的开口部分25b，以便位于栅电极和LDD区之上; 通过开口部中的导电膜形成第二栅电极26b，以覆盖栅电极和LDD区; 以及在第二层间绝缘膜上的像素电极26a; 去除接触孔中的栅极绝缘膜; 以及形成连接到每个源极区域和漏极区域的布线27,28。

103. 发明申请

US20050142702A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050142702A1
公开(公告)日：2005-06-30
申请号：US11012171
申请日：2004-12-16
申请人： Hideto Ohnuma , Masayuki Sakakura , Yasuhiro Mitani , Takuya Matsuo , Hidehito Kitakado
发明人： Hideto Ohnuma , Masayuki Sakakura , Yasuhiro Mitani , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L29/786 , H01L21/20 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/10 , H01L21/00 , H01L29/76 , H01L31/036 , H01L31/112
CPC分类号： H01L29/66757 , H01L21/02532 , H01L21/02667 , H01L21/02672 , H01L21/02686 , H01L27/12 , H01L27/1277
摘要： A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof. A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.
摘要翻译：具有抑制空腔制造的结晶半导体膜的半导体器件及其制造方法。根据本发明的半导体器件的制造方法包括以下步骤：在具有绝缘表面的衬底上形成非晶硅膜，向非晶硅膜中添加用于促进结晶的Ni等金属元素，进行热处理，使结晶非晶硅膜，使得在基板上形成结晶硅膜，通过含有机溶剂和氟化物的溶液进行热处理，除去形成在结晶硅膜表面的氧化硅膜，并照射激光或强力光结晶硅膜。

104. 发明申请

US20050133862A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050133862A1
公开(公告)日：2005-06-23
申请号：US11010389
申请日：2004-12-14
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/76 , H01L21/3205
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露于第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

105. 发明授权

US5929486A CMOS device having a reduced short channel effect 失效
标题翻译： CMOS器件具有减小的短沟道效应
公开(公告)号：US5929486A
公开(公告)日：1999-07-27
申请号：US956290
申请日：1997-10-23
申请人： Hidehito Kitakado
发明人： Hidehito Kitakado
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/76 , H01L29/94
CPC分类号： H01L27/0928 , H01L21/823807
摘要： A CMOS device includes a first MOS transistor of a surface channel type and a second MOS transistor of a buried channel type on a common substrate wherein a doped layer is provided underneath a first channel layer of the first MOS transistor and a second channel layer of the second MOS transistor, such that the first channel layer is provided at a level closer to a principal surface of the substrate as compared with source and drain regions of the first and second MOS transistors.
摘要翻译： CMOS器件包括在公共衬底上的表面沟道型的第一MOS晶体管和埋入沟道型的第二MOS晶体管，其中掺杂层设置在第一MOS晶体管的第一沟道层的下方，第二沟道层第二MOS晶体管，使得与第一和第二MOS晶体管的源极和漏极区域相比，第一沟道层设置在更靠近衬底的主表面的水平处。

106. 发明授权

US5041847A Thermal head 失效
标题翻译：热头
公开(公告)号：US5041847A
公开(公告)日：1991-08-20
申请号：US570397
申请日：1990-08-21
申请人： Shoji Matsumoto , Daisuke Kosaka , Masaaki Yoshida , Hidehito Kitakado , Kenji Fujita
发明人： Shoji Matsumoto , Daisuke Kosaka , Masaaki Yoshida , Hidehito Kitakado , Kenji Fujita
IPC分类号： B41J2/335
CPC分类号： B41J2/3353 , B41J2/33535 , B41J2/3355 , B41J2/3357
摘要： A thermal head comprising a substrate, a heat-resistant dielectric resin layer disposed on the substrate, a resistor layer disposed on the resin layer for forming a plurality of heating elements and an electrode layer disposed on the resistor layer for forming electrodes connecting to the heating elements. A protection film covers an end of the substrate and each end of the layers which is substantially in the same plane as the substrate end.
摘要翻译：一种热敏头，包括基底，设置在基底上的耐热电介质树脂层，设置在用于形成多个加热元件的树脂层上的电阻层和设置在电阻层上的电极层，用于形成连接到加热的电极元素。保护膜覆盖基板的端部，并且层的每个端部基本上在与基板端部相同的平面中。

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