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101. 发明申请

US20070047354A1 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US20070047354A1
公开(公告)日：2007-03-01
申请号：US11511262
申请日：2006-08-29
申请人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
发明人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
IPC分类号： G11C7/02
CPC分类号： G11C5/147 , G11C5/02 , G11C7/02 , H01L24/48 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2924/00014 , H01L2924/10161 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.
摘要翻译：半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。第一半导体器件包括第一电极。第二半导体器件包括第二电极。参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

102. 发明授权

US07095661B2 Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM 有权
标题翻译：半导体存储器模块，存储器系统，电路，半导体器件和DIMM
公开(公告)号：US07095661B2
公开(公告)日：2006-08-22
申请号：US11019274
申请日：2004-12-23
申请人： Hideki Osaka , Yoji Nishio , Seiji Funaba
发明人： Hideki Osaka , Yoji Nishio , Seiji Funaba
IPC分类号： G11C99/00
CPC分类号： G11C29/028 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C11/4093 , G11C29/02 , G11C29/50012
摘要： There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.
摘要翻译：存在的问题是，由于DIMM中的C / A信号通过DIMM中的寄存器分配到相应的DRAM，DQ信号直接从DIMM中的端子连接，因此它们的时序难以同步。提供用于加速高速运行的DIMM的C / A信号的寄存器，寄存器的布线设置为菊花链布线。然后，通过设置在DRAM中的定时调整电路，根据DRAM的位置而不同的C / A信号和时钟信号之间的布线延迟时间差使得从寄存器的延迟时间之和并且由于定时调整电路引起的延迟量等于最远的DRAM的延迟时间。

103. 发明授权

US06937494B2 Memory module, memory chip, and memory system 失效
公开(公告)号：US06937494B2
公开(公告)日：2005-08-30
申请号：US10699628
申请日：2003-10-31
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/16 , G11C5/00 , G11C5/06 , G11C11/401
CPC分类号： G11C5/063
摘要： A memory module includes at least one CAR and a plurality of DRAMs provided so as to be close and adjacent to one another on one face and the other face of a module substrate. The DRAMs are divided into a plurality of memory groups. Memory groups adjacent to each other of these memory groups are paired with each other. One of this pair is a 1-ranked memory group and the other is a 2-ranked memory group. This pair of the memory groups is connected to the CAR via short wiring with a T-branch structure having a short stub. One of the pair of the memory groups on the signal-reception side functions as an open end. Active termination is performed by a termination resistor of the other of the pair of the memory groups on the signal-non-reception side. Subsequently, signal reflections can be reduced.

104. 发明申请

US20050105318A1 Memory module, memory chip, and memory system 失效
标题翻译：内存模块，内存芯片和内存系统
公开(公告)号：US20050105318A1
公开(公告)日：2005-05-19
申请号：US10699628
申请日：2003-10-31
申请人： Seiji Funaba , Yoji Nishio
发明人： Seiji Funaba , Yoji Nishio
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/16 , G11C5/00 , G11C5/06 , G11C11/401
CPC分类号： G11C5/063
摘要： A memory module includes at least one CAR and a plurality of DRAMs provided so as to be close and adjacent to one another on one face and the other face of a module substrate. The DRAMs are divided into a plurality of memory groups. Memory groups adjacent to each other of these memory groups are paired with each other. One of this pair is a 1-ranked memory group and the other is a 2-ranked memory group. This pair of the memory groups is connected to the CAR via short wiring with a T-branch structure having a short stub. One of the pair of the memory groups on the signal-reception side functions as an open end. Active termination is performed by a termination resistor of the other of the pair of the memory groups on the signal-non-reception side. Subsequently, signal reflections can be reduced.
摘要翻译：存储器模块包括至少一个CAR和多个DRAM，其设置成在模块基板的一个面和另一个面上彼此靠近并相邻。 DRAM被分成多个存储器组。这些存储器组彼此相邻的存储器组彼此配对。这对之一是1排列的内存组，另一个是2排的内存组。这对存储器组通过具有短截线的T形支路结构的短路连接到CAR。信号接收侧的一对存储器组之一用作开放端。有源终端由信号非接收侧的一对存储器组中的另一个的终端电阻执行。随后，可以减少信号反射。

105. 发明授权

US06862246B2 Semiconductor apparatus which prevents generating noise and being influenced by noise 有权
标题翻译：防止产生噪声并受噪声影响的半导体装置
公开(公告)号：US06862246B2
公开(公告)日：2005-03-01
申请号：US10454404
申请日：2003-06-04
申请人： Seiji Funaba , Yoji Nishio , Hiroaki Ikeda
发明人： Seiji Funaba , Yoji Nishio , Hiroaki Ikeda
IPC分类号： G06F1/12 , G11C7/10 , G11C7/22 , G11C11/407 , H01L21/822 , H01L27/04 , H03K3/03 , H03K5/00 , H03L7/00 , H03L7/089 , H03L7/091 , H03L7/099 , G11C8/00
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , H03K3/0322 , H03K2005/00078 , H03K2005/00208 , H03L7/0895 , H03L7/091 , H03L7/0995
摘要： The present invention provides a semiconductor apparatus including an internal clock generating unit and a data storing unit. The internal clock generating unit generates an internal clock signal based on an external clock signal and a clock control signal. The data storing unit which operates data processing based on the internal clock signal. The internal clock generating unit carries out synchronous control such that the internal clock signal is synchronized with the external clock signal. The data storing unit generates the clock control signal based on the data processing and outputs the clock control signal to the internal clock generating unit to control the synchronous control. The data storing unit may controls the internal clock generating unit such that the synchronous control is adjourned or restrained temporarily while the data processing is a data reading process.
摘要翻译：本发明提供一种包括内部时钟生成单元和数据存储单元的半导体装置。内部时钟发生单元基于外部时钟信号和时钟控制信号产生内部时钟信号。数据存储单元，其基于内部时钟信号进行数据处理。内部时钟发生单元执行同步控制，使得内部时钟信号与外部时钟信号同步。数据存储单元基于数据处理生成时钟控制信号，并将时钟控制信号输出到内部时钟发生单元，以控制同步控制。数据存储单元可以控制内部时钟生成单元，使得在数据处理是数据读取处理的同时控制暂时中止或暂时抑制。

106. 发明授权

US06661092B2 Memory module 有权
标题翻译：内存模块
公开(公告)号：US06661092B2
公开(公告)日：2003-12-09
申请号：US10205040
申请日：2002-07-25
申请人： Kayoko Shibata , Yoji Nishio
发明人： Kayoko Shibata , Yoji Nishio
IPC分类号： H01L2334
CPC分类号： G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.
摘要翻译：存储器模块设置有用作阻抗调节器的电阻器，其直接或间接地连接到C / A寄存器的输出晶体管的输出端子。该电阻调节从C / A总线的输入端子观察的C / A寄存器的输出阻抗，使得输出阻抗在从C / A寄存器输出的内部信号的工作电压范围内变得基本恒定。存储器模块还具有用作上升时间/下降时间调节器的电容器，其将内部信号的上升时间和下降时间调整到特定值，从而获得令人满意的波形。

107. 发明授权

US06619340B2 Liquid metering and filling lifter for containers 失效
标题翻译：容器用液体计量和灌装升降机
公开(公告)号：US06619340B2
公开(公告)日：2003-09-16
申请号：US09960976
申请日：2001-09-25
申请人： Masakatsu Kondo , Yoji Nishio , Yasuji Fujikawa , Michio Ueda
发明人： Masakatsu Kondo , Yoji Nishio , Yasuji Fujikawa , Michio Ueda
IPC分类号： B65B4342
CPC分类号： B65B43/59 , B65B59/02
摘要： A liquid metering and filling lifter for use with different kinds of containers (C) having different heights for moving the container (C) upward and downward with a stroke corresponding to the height of the container (C) in filling a liquid into the container, the lifter comprising a container pushing-up vertical lift rod (32) disposed below a filling nozzle (13) above a bed (11) and extending through the bed (11), the lift rod (32) having a container support (31) fixed to an upper end thereof, a container pushing-down vertical lift rod (34) extending through the bed (11) at one side of the lift rod (32) and having a container holder (33) fixed to an upper end thereof, and coupling means (35) disposed below the bed (11) for coupling the two lift rods (32), (34) to make the lift rods movable upward or downward together and uncoupling the lift rods (32), (34) to make the lift rods movable upward or downward individually.
摘要翻译：一种用于不同种类的容器（C）的液体计量和填充提升器，其具有不同的高度，用于在将液体填充到容器中时以对应于容器（C）的高度的行程向上和向下移动，所述提升器包括设置在床（11）上方并且延伸穿过所述床（11）的填充喷嘴（13）下方的容器上推垂直提升杆（32），所述提升杆（32）具有容器支撑件（31）固定在其上端，在提升杆（32）的一侧延伸穿过床（11）并且具有固定到其上端的容器保持器（33）的容器下推垂直提升杆（34）以及设置在所述床（11）下方的联接装置（35），用于联接所述两个提升杆（32），（34），以使提升杆可以一起向上或向下移动在一起，并使提升杆（32），（34）提升杆可以单独上下移动。

108. 发明授权

US06574154B2 Data transmitter 有权
公开(公告)号：US06574154B2
公开(公告)日：2003-06-03
申请号：US09988152
申请日：2001-11-19
申请人： Takashi Sato , Yoji Nishio , Yoshinobu Nakagome
发明人： Takashi Sato , Yoji Nishio , Yoshinobu Nakagome
IPC分类号： G11C700
CPC分类号： G11C11/4093 , G11C7/04 , G11C7/1006 , G11C7/1072 , G11C7/22 , G11C2207/2254
摘要： A large difference in the lengths of the passages or a large difference in the load capacitances inclusive of parasitic elements of parallel data wirings can cause differences in the propagation time of data on the parallel data wirings. The invention provides a simultaneous arrival judging circuit for comparing phases of part or whole bits of data received from the parallel data wirings, and a timing adjusting mechanism for adjusting phases among parallel bits of the received data based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at a receiver.

109. 发明授权

US06411539B1 Memory system 有权
公开(公告)号：US06411539B1
公开(公告)日：2002-06-25
申请号：US09802842
申请日：2001-03-12
申请人： Seiji Funaba , Yoji Nishio , Yoshinobu Nakagome
发明人： Seiji Funaba , Yoji Nishio , Yoshinobu Nakagome
IPC分类号： G11C506
摘要： A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.

110. 发明授权

US6160275A Semiconductor gate array device 失效
标题翻译：半导体门阵列器件
公开(公告)号：US6160275A
公开(公告)日：2000-12-12
申请号：US692253
申请日：1996-08-05
申请人： Yoji Nishio , Yasuo Kaminaga , Isamu Kobayashi , Yoshihiko Yamamoto , Nozomi Horino , Kousaku Hirose
发明人： Yoji Nishio , Yasuo Kaminaga , Isamu Kobayashi , Yoshihiko Yamamoto , Nozomi Horino , Kousaku Hirose
IPC分类号： H01L27/118 , H01L27/10
CPC分类号： H01L27/11807
摘要： In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines. Additionally, in order to present a semiconductor integrated device having a static type RAM that has realized with its simple structure a shortening of the memory cycle, a RAM is constructed by having memory cells, in which each is composed of a pair of transfer MOSFETs, which both of the MOSFETs are turned on during the write-in operation and one of the MOSFETs is turned on during the read-out operation, is located in between a complementary data line and an input/output node that has a complementary relationship with an information storage part comprised by a pair of inverter circuits in which the inputs and outputs are mutually cross-connected. By constructing in this way, it becomes possible to speed up the write-in operation with accuracy by having a complementary write-in signal received from a pair of the complementary lines during the read-out operation, and it becomes possible to obtain read-out signals rapidly and to prevent write-in errors caused by the pre-read-out potential of the data line because the information storage part is connected only to one of the data lines through one of the transfer gates during the read-out operation.
摘要翻译：为了呈现具有高存储密度和高速逻辑电路的主片式LSI的基本单元，基本单元由每对PMOS 1，NMOS 4，PMOS 7和NMOS 10组成，并且三个接触孔 - 除了接触孔17之外，因为连接到GND电源线51和53或Vcc电源线50和52的每个MOS的MOS沟道宽度W内的接触孔形成在垂直方向上到每个电力线。此外，为了呈现具有通过其简单结构实现的具有简化结构的静态型RAM的半导体集成器件，缩短了存储器周期，RAM通过具有存储单元构成，其中每个存储单元由一对转移MOSFET组成，其中两个MOSFET在写入操作期间导通，并且在读出操作期间MOSFET中的一个导通，位于互补数据线与具有互补关系的输入/输出节点之间信息存储部分由输入和输出相互交叉连接的一对反相器电路组成。通过以这种方式构造，可以通过在读出操作期间具有从一对互补线接收的互补写入信号来准确地加速写入操作，并且可以获得读取操作，并且防止由于数据线的预读出电位引起的写入错误，因为信息存储部分在读出操作期间仅通过一个传输门连接到一条数据线。

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