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101. 发明授权

US4760281A Clock signal generating circuit 失效
标题翻译：时钟信号发生电路
公开(公告)号：US4760281A
公开(公告)日：1988-07-26
申请号：US11947
申请日：1987-02-06
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： H03K5/02 , H03K5/135 , H03K17/04 , H03K19/017 , H03K19/096 , H03K19/01
CPC分类号： H03K19/01735
摘要： In a clock signal generating circuit for a semiconductor large scale integrated circuit, the clock signal generating circuit includes: a P-channel transistor and a first N-channel transistor, each connected in series between a positive side power source line and a ground side power source line; a second N-channel transistor connected between a common connection point of the P-channel transistor and the first N-channel transistor and a gate of the first N-channel transistor through a node, and a clock signal is applied to a gate of the second N-channel transistor. A capacitor is connected between the gate of the first N-channel transistor and a gate of the P-channel transistor; and a bootstrap capacitor is connected to the common connection point.
摘要翻译：在半导体大规模集成电路的时钟信号发生电路中，时钟信号发生电路包括：P沟道晶体管和第一N沟道晶体管，其串联连接在正侧电源线和接地侧电源源线; 连接在P沟道晶体管的公共连接点和第一N沟道晶体管之间的第二N沟道晶体管和通过节点的第一N沟道晶体管的栅极，并且时钟信号被施加到第二N沟道晶体管。电容器连接在第一N沟道晶体管的栅极和P沟道晶体管的栅极之间; 并且自举电容器连接到公共连接点。

102. 发明授权

US4679214A Shift register for refreshing a MIS dynamic memory 失效
标题翻译：移位寄存器用于刷新MIS动态内存
公开(公告)号：US4679214A
公开(公告)日：1987-07-07
申请号：US648506
申请日：1984-09-10
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： G11C19/00 , G11C19/08 , G11C19/18 , G11C19/28
CPC分类号： G11C19/00 , G11C19/184 , G11C19/28
摘要： A shift register having a simple circuit structure and used, for example, in a dynamic RAM device for a refresh operation. The shift register includes a plurality of circuit stages mutually connected in cascade. Each of the circuit stages includes a first transistor, for a transfer gate, which is turned on and off by a first clock signal and to which is input the output signal of the previous circuit stage. A second transistor is provided whose gate electrode is connected to the output of the first transistor, whose drain or source electrode receives a second clock signal having a different phase from the first clock signal, and whose source or drain electrode outputs an output signal. Each circuit stage also includes a reset circuit for rendering the input portion of the first transistor to a reset condition on the basis of the output signal, thereby sequentially transmitting data through each circuit stage.
摘要翻译：一种移位寄存器，具有简单的电路结构，并且例如用于用于刷新操作的动态RAM装置中。移位寄存器包括级联相互连接的多个电路级。每个电路级包括用于传输门的第一晶体管，其通过第一时钟信号导通和截止，并且输入到先前电路级的输出信号。提供了第二晶体管，其栅电极连接到第一晶体管的输出，其漏极或源极接收与第一时钟信号具有不同相位的第二时钟信号，并且其源极或漏极输出输出信号。每个电路级还包括一个复位电路，用于根据输出信号将第一晶体管的输入部分渲染到复位状态，由此顺序地通过每个电路级发送数据。

103. 发明授权

US4572977A Range checking comparator 失效
标题翻译：范围检查比较器
公开(公告)号：US4572977A
公开(公告)日：1986-02-25
申请号：US560953
申请日：1983-12-13
申请人： Yoshihiro Takemae , Yasuo Suzuki
发明人： Yoshihiro Takemae , Yasuo Suzuki
IPC分类号： H03K3/0233 , H03K3/356 , H03K5/08 , H03K5/24 , G01R19/165 , G11C7/06
CPC分类号： H03K3/356017 , H03K3/35606
摘要： A comparator includes a first terminal, a second terminal, a first flip-flop circuit which inverts when the voltage applied to the first terminal becomes larger by .DELTA.V.sub.1 than the voltage applied to the second terminal, a third terminal, a fourth terminal, and a second flip-flop circuit which inverts when the voltage applied to the third terminal becomes smaller by .DELTA.V.sub.2 than the voltage applied to the fourth terminal. The comparator further includes a first switching circuit and a second switching circuit which, respectively, connect the first terminal and the fourth terminal to a voltage source to be compared, a third switching circuit and a fourth switching circuit which connect the second terminal and the third terminal to a reference voltage source. Also included is a fifth switching circuit which is commonly connected to the first flip-flop circuit and the second flip-flop circuit.
摘要翻译：比较器包括第一端子，第二端子，当施加到第一端子的电压比施加到第二端子的电压DELTA V1变大时的第一触发器电路，第三端子，第四端子和第二触发器电路，当施加到第三端子的电压变得比施加到第四端子的电压减小DELTA V2时反相。比较器还包括分别将第一端子和第四端子连接到要比较的电压源的第一开关电路和第二开关电路，连接第二端子和第三端子的第三开关电路和第四开关电路端子到参考电压源。还包括第五开关电路，其共同连接到第一触发器电路和第二触发器电路。

104. 发明授权

US4546457A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4546457A
公开(公告)日：1985-10-08
申请号：US439591
申请日：1982-11-05
申请人： Shigeki Nozaki , Yoshihiro Takemae
发明人： Shigeki Nozaki , Yoshihiro Takemae
IPC分类号： G11C11/419 , G11C7/06 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/40
CPC分类号： G11C11/4087 , G11C7/06
摘要： A metal-insulator semiconductor dynamic memory device comprising sense amplifiers arrayed on a semiconductor substrate and column decoders. Each of the column decode being provided for a plurality of sense amplifiers and selecting one or more sense amplifiers from the plurality of sense amplifiers, the column decoders being dispersed on both sides of the arrayed sense amplifiers. A plurality of control signal lines which, in order to select the sense amplifiers, control gate elements connected between bit lines connected to the sense amplifiers and data bus lines and which are disposed on both sides of the arrayed sense amplifiers. Conducting lines are also disposed between the sense amplifiers and deliver signals from the control signal lines, for selecting sense amplifiers to the gate elements on the opposite side of the control signal lines with regard to the arrayed sense amplifiers.
摘要翻译：包括排列在半导体衬底和列解码器上的读出放大器的金属 - 绝缘体半导体动态存储器件。每个列解码被提供给多个读出放大器并且从多个读出放大器中选择一个或多个感测放大器，列解码器分散在排列的读出放大器的两侧。多个控制信号线，为了选择读出放大器，控制栅极元件连接在连接到读出放大器的位线和数据总线之间，并且布置在阵列读出放大器的两侧。传导线还设置在感测放大器之间并且传送来自控制信号线的信号，用于选择感测放大器到控制信号线相对于阵列读出放大器的相反侧的门元件。

105. 发明授权

US4532613A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4532613A
公开(公告)日：1985-07-30
申请号：US356487
申请日：1982-03-09
申请人： Yoshihiro Takemae , Tomio Nakano , Tsuyoshi Ohira
发明人： Yoshihiro Takemae , Tomio Nakano , Tsuyoshi Ohira
IPC分类号： G11C11/407 , G11C11/409 , G11C11/4093 , G11C11/40
CPC分类号： G11C11/4093
摘要： In a semiconductor memory device including an output buffer circuit receiving data signals read out from a memory cell array, an output stage MOS transistor being turned ON and OFF according to the output signals of the output buffer circuit, and an output buffer enable (OBE) signal generator circuit for generating an OBE signal which is used as the voltage supply to the output stage of the output buffer circuit, a V.sub.BS voltage generator circuit is provided for generating a voltage V.sub.BS higher than the voltage source V.sub.CC preceding the rising up of the OBE signal, which voltage V.sub.BS is used as a voltage supply to the output stage of the OBE signal generator circuit, whereby the OBE signal is formed as a voltage waveform which rises rapidly up to a level higher than the voltage source V.sub.CC.
摘要翻译：在包括从存储单元阵列读出的数据信号的输出缓冲电路的半导体存储器件中，输出级MOS晶体管根据输出缓冲电路的输出信号而导通和截止，而输出缓冲器使能（OBE）信号发生器电路，用于产生用作向输出缓冲电路的输出级的电压供给的OBE信号，提供VBS电压发生器电路，用于产生比OBE上升之前的电压源VCC高的电压VBS 信号，哪个电压VBS被用作到OBE信号发生器电路的输出级的电压供应，由此OBE信号形成为快速上升到高于电压源VCC的电平的电压波形。

106. 发明授权

US4504929A Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US4504929A
公开(公告)日：1985-03-12
申请号：US444499
申请日：1982-11-24
申请人： Yoshihiro Takemae , Tsuyoshi Ohira , Seiji Enomoto
发明人： Yoshihiro Takemae , Tsuyoshi Ohira , Seiji Enomoto
IPC分类号： G11C11/401 , G11C11/4091 , G11C29/00 , G11C29/02 , G11C29/50 , G11C11/40
CPC分类号： G11C29/026 , G11C11/4091 , G11C29/02 , G11C29/50 , G11C11/401 , G11C2029/5004
摘要： A dynamic semiconductor memory device provides a selected real cell, which is connected to a first of a pair of bit lines connected to a sense amplifier, and a dummy cell which is connected to a second of the pair of bit lines so as to perform a read-out operation. The dynamic semiconductor memory cell further provides an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by the read-out operation. The dynamic semiconductor cell can also provide a write-in circuit for charging the selected real cell through the bit line. A test power source pad is provided in the active restore circuit or the write in circuit so that when the reference level of the real cell is tested an optional power source can be applied from the test power source pad instead of from a normal power source.
摘要翻译：动态半导体存储器件提供选择的实数单元，其连接到连接到读出放大器的一对位线中的第一个，以及连接到所述一对位线中的第二位的虚拟单元，以执行读出操作。动态半导体存储单元进一步提供有源恢复电路，用于提升位线对的位线电位，该位线位于通过读出操作增加电位差的位线对的较高电位侧。动态半导体单元还可以提供用于通过位线对所选择的真实单元进行充电的写入电路。在有源恢复电路或写入电路中提供测试电源焊盘，使得当测试真实单元的参考电平时，可以从测试电源焊盘而不是普通电源施加可选的电源。

107. 发明授权

US08683165B2 Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips 有权
标题翻译：具有多种类型的存储器芯片的存储器系统和用于控制存储器芯片的存储器控制器
公开(公告)号：US08683165B2
公开(公告)日：2014-03-25
申请号：US12631240
申请日：2009-12-04
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C8/00 , G11C8/18
CPC分类号： G06F3/0626 , G06F3/0658 , G06F3/0659 , G06F3/068 , G06F3/0688 , G06F12/00 , G06F12/0246 , G06F12/0623 , G06F13/1694 , G06F2212/7201 , G11C5/04 , G11C7/1072
摘要： A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.
摘要翻译：存储器控制器根据要操作的存储器芯片的操作规范，将从控制器输出的控制器输出信号转换为存储器输入信号，并通过公共总线将结果输出到存储器芯片。存储器控制器还通过公共总线接收从存储器芯片输出的存储器输出信号，并将接收的信号转换成可接收到控制器的控制器输入信号。这允许单个存储器控制器访问多种类型的存储器芯片。结果，存储器控制器可以减小芯片尺寸，降低存储器系统的成本。

108. 发明授权

US08541815B2 High electron mobility transistor circuit 有权
标题翻译：高电子迁移率晶体管电路
公开(公告)号：US08541815B2
公开(公告)日：2013-09-24
申请号：US13351869
申请日：2012-01-17
申请人： Yoshihiro Takemae , Tsutomu Hosoda , Toshiya Sato
发明人： Yoshihiro Takemae , Tsutomu Hosoda , Toshiya Sato
IPC分类号： H01L29/66
CPC分类号： H01L29/778 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/402 , H01L29/404 , H01L29/41758 , H01L29/41766 , H01L29/4236 , H01L29/66462 , H01L29/7787 , H01L2924/0002 , H01L2924/00
摘要： A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor.
摘要翻译：晶体管电路包括具有负阈值电压的第一高电子迁移率晶体管和第二高电子迁移率晶体管，其中第二高电子迁移率晶体管的源极耦合到第一高电子迁移率晶体管的栅极，以及栅极第二高电子迁移率晶体管耦合到第一高电子迁移率晶体管的源极。

109. 发明授权

US08431965B2 Control circuit of transistor and method 有权
标题翻译：晶体管的控制电路及方法
公开(公告)号：US08431965B2
公开(公告)日：2013-04-30
申请号：US13310144
申请日：2011-12-02
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： H03K17/284 , G05F1/575
CPC分类号： H03K17/08122
摘要： A control circuit, which controls a transistor including a gate and a field plate, includes: a detecting circuit which detects a driving timing to drive the transistor; a timing controlling circuit which controls a first driving timing to drive the gate and a second driving timing to drive the field plate, in response to the driving timing; and a driving circuit which drives the gate in response to the first driving timing, and drives the field plate in response to the second driving timing.
摘要翻译：控制包括栅极和场板的晶体管的控制电路包括：检测电路，其检测驱动晶体管的驱动时序; 响应于驱动定时，控制第一驱动定时以驱动门的定时控制电路和驱动场板的第二驱动定时; 以及驱动电路，其响应于第一驱动定时驱动门，并且响应于第二驱动定时驱动场板。

110. 发明申请

US20120268091A1 SWITCHING CIRCUIT DEVICE AND POWER SUPPLY DEVICE HAVING SAME 审中-公开
标题翻译：切换电路装置和具有相同功能的电源装置
公开(公告)号：US20120268091A1
公开(公告)日：2012-10-25
申请号：US13361216
申请日：2012-01-30
申请人： Yoshihiro Takemae
发明人： Yoshihiro Takemae
IPC分类号： G05F1/10
CPC分类号： H02M3/158 , H02M1/44 , H03K17/164
摘要： A switching circuit device provided between a first node and a second node within a power supply circuit, an inductor being coupled to the first or second node, the switching circuit device has: a first transistor that is provided between the first node and the second node and has a first gate width; a second transistor that is provided in parallel with the first transistor between the first node and the second node and has a second gate width larger than the first gate width; and a driving signal generation circuit, which, in response to a control signal generated according to an output voltage of the power supply circuit, outputs a first driving signal which drives the first transistor on and off, and a second driving signal which drives the second transistor on and off, with different timings between the first driving signal output and the second driving signal output.
摘要翻译：一种切换电路装置，设置在电源电路内的第一节点和第二节点之间，电感器耦合到第一或第二节点，开关电路装置具有：设置在第一节点和第二节点之间的第一晶体管并具有第一栅极宽度; 第二晶体管，其与第一晶体管并联设置在第一节点和第二节点之间，并且具有大于第一栅极宽度的第二栅极宽度; 以及驱动信号生成电路，其响应于根据所述电源电路的输出电压而生成的控制信号，输出驱动所述第一晶体管的导通和截止的第一驱动信号，以及驱动所述第二驱动信号的第二驱动信号晶体管的导通和截止，具有第一驱动信号输出和第二驱动信号输出之间的不同定时。

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