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101. 发明授权

US09069624B1 Systems and methods for DSP block enhancement 有权
标题翻译： DSP块增强的系统和方法
公开(公告)号：US09069624B1
公开(公告)日：2015-06-30
申请号：US13555907
申请日：2012-07-23
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/53
CPC分类号： G06F7/5324 , G06F7/53
摘要： Methods and systems for signal processing using processing blocks are provided. In one embodiment of the disclosure, there are provided a plurality of multiplier circuitries and control circuitry configured to multiply numbers AB and CD. The number AB includes components A and B, and the component A includes subcomponents AH and AL. The number CD includes components C and D, and the component C includes subcomponents CH and CL. The control circuitry is configured to compute a partial product AD based on multiplying D and AL using a first multiplier circuitry and based on multiplying D and AH the using a first multiplier module of a second multiplier circuitry. The control circuitry is also configured to compute a partial product CB based on B and CL using a third multiplier circuitry and based on multiplying B and the CH using a second multiplier module of the second multiplier circuitry.
摘要翻译：提供了使用处理块进行信号处理的方法和系统。在本公开的一个实施例中，提供了多个乘法器电路和控制电路，其被配置为将数字AB和CD相乘。数字AB包括组件A和B，组件A包括子组件AH和AL。数字CD包括组件C和D，组件C包括子组件CH和CL。控制电路被配置为基于使用第一乘法器电路乘法D和AL并且基于乘法D和AH使用第二乘法器电路的第一乘法器模块来计算部分乘积AD。控制电路还被配置为使用第三乘法器电路基于B和CL计算部分乘积CB，并且基于使用第二乘法器电路的第二乘法器模块乘以B和CH。

102. 发明授权

US09032277B1 Parallel low and asymmetric rate Reed Solomon coding 有权
标题翻译：并行低和非对称速率里德所罗门编码
公开(公告)号：US09032277B1
公开(公告)日：2015-05-12
申请号：US13469741
申请日：2012-05-11
申请人： Martin Langhammer , Chuck Rumbolt
发明人： Martin Langhammer , Chuck Rumbolt
IPC分类号： H03M13/00 , H03M13/03 , H03M13/15
CPC分类号： H03M13/1515 , H03M13/153 , H03M13/1545 , H03M13/1555 , H03M13/157 , H03M13/1585 , H03M13/6502
摘要： In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.
摘要翻译：在所公开的系统，装置和方法的布置中，根据第二数量的校验符号接收编码有第一数量的校验符号的码字并对其进行非对称处理，其中第二数量的校验符号小于第一数目的检验符号，以产生误差定位多项式和误差评估器多项式。通过输出第一多项式项和第二多项式项来产生误差定位多项式的导数，其中第二多项式项是常数。误差定位多项式的导数使用可变有限域乘法器产生，而不使用分频器。

103. 发明授权

US08886696B1 Digital signal processing circuitry with redundancy and ability to support larger multipliers 有权
标题翻译：数字信号处理电路具有冗余和支持较大乘法器的能力
公开(公告)号：US08886696B1
公开(公告)日：2014-11-11
申请号：US12380853
申请日：2009-03-03
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/52 , H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： G06F7/52 , G06F7/5324 , G06F7/5443 , G06F11/08 , G06F2207/382 , H01L25/00 , H01L2924/0002 , H03K19/173 , H03K19/177 , H01L2924/00
摘要： Digital signal processing (“DSP”) circuit blocks that include multipliers of a certain basic size are augmented to enable the DSP block to perform multiplications that are larger than the basic multiplier size would otherwise permit. In some embodiments, the larger multiplication can have less than full precision. In other embodiments, the larger multiplication can have full precision by making use of some capabilities of a second DSP block.
摘要翻译：包括特定基本尺寸的乘法器的数字信号处理（“DSP”）电路块被增加以使得DSP块执行大于基本乘法器大小否则将允许的乘法。在一些实施例中，较大的乘法可具有小于全精度。在其他实施例中，通过利用第二DSP块的某些能力，较大乘法可以具有完全的精度。

104. 发明授权

US08812573B2 Calculation of trigonometric functions in an integrated circuit device 有权
标题翻译：集成电路设备中三角函数的计算
公开(公告)号：US08812573B2
公开(公告)日：2014-08-19
申请号：US13159614
申请日：2011-06-14
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/38
CPC分类号： G06F7/548 , G06F1/03 , G06F7/483 , G06F7/5446 , G06F2101/04
摘要： Circuitry for computing a trigonometric function of an input includes circuitry for relating the input to another value to generate an intermediate value, circuitry for selecting one of the input and the intermediate value as a trigonometric input value, circuitry for determining respective initial values of a plurality of trigonometric functions for the trigonometric input value, and circuitry for deriving, based at least in part on a trigonometric identity, a final value of the first trigonometric function from the respective initial values of the plurality of trigonometric functions. The trigonometric function may be any of sine, cosine and tangent and their inverse functions. The trigonometric identities used allow a computation of a trigonometric function to be broken into pieces that either are easier to perform or can be performed more accurately.
摘要翻译：用于计算输入的三角函数的电路包括用于将输入与另一值相关以产生中间值的电路，用于选择输入和中间值之一作为三角输入值的电路，用于确定多个的相应初始值的电路用于三角输入值的三角函数的电路，以及用于至少部分地基于三角形标识从多个三角函数的相应初始值推导出第一三角函数的最终值的电路。三角函数可以是任何正弦，余弦和正切以及它们的反函数。所使用的三角形身份允许将三角函数的计算分解成更容易执行或可以更准确地执行的片段。

105. 发明授权

US08805916B2 Digital signal processing circuitry with redundancy and bidirectional data paths 有权
标题翻译：具有冗余和双向数据路径的数字信号处理电路
公开(公告)号：US08805916B2
公开(公告)日：2014-08-12
申请号：US12380841
申请日：2009-03-03
申请人： Martin Langhammer , Yi-Wen Lin , Keone Streicher
发明人： Martin Langhammer , Yi-Wen Lin , Keone Streicher
IPC分类号： G06F7/38 , G06F7/00 , G06F15/00 , H03K19/173 , H03K19/177 , H01L25/00 , H03K5/1252 , G06F7/53
CPC分类号： H03K5/1252 , G06F7/5324 , G06F2207/382 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect).
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。

106. 发明授权

US08707143B1 Multiplication-based reed-solomon encoding architecture 有权
标题翻译：基于乘法的reed-solomon编码架构
公开(公告)号：US08707143B1
公开(公告)日：2014-04-22
申请号：US13158965
申请日：2011-06-13
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H03M13/03 , H03M13/15 , H04L1/00 , G11B20/18
CPC分类号： H03M13/1515 , G11B20/1833 , H03M13/611 , H03M13/616 , H03M13/6561 , H04L1/0057
摘要： Circuitry for generating a first number of Reed-Solomon check symbols from a second number of input data symbols includes storage for a plurality of generator coefficients, a plurality of multipliers, each of the multipliers having a data symbol input, and a coefficient input connected to the storage, and having an output. The circuitry also includes accumulator circuitry that accumulates outputs of the multipliers to generate the check symbols. The circuitry can be provided in fixed logic, or configured in a programmable integrated circuit device, such as a programmable logic device.
摘要翻译：用于从第二数量的输入数据符号生成第一数目的Reed-Solomon检查符号的电路包括用于多个发生器系数的存储，多个乘法器，每个乘法器具有数据符号输入，以及系数输入连接到存储，并具有输出。电路还包括累积电路，其累加乘法器的输出以产生校验符号。电路可以以固定逻辑提供，或者配置在诸如可编程逻辑器件的可编程集成电路器件中。

107. 发明授权

US08649518B1 Implementing CSA cryptography in an integrated circuit device 有权
标题翻译：在集成电路设备中实现CSA加密
公开(公告)号：US08649518B1
公开(公告)日：2014-02-11
申请号：US13369821
申请日：2012-02-09
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： H04K1/00 , H04L29/06
CPC分类号： H04L63/0428 , H04L9/0637 , H04L9/065 , H04L2209/125 , H04L2209/60
摘要： A method and circuitry for implementing CSA fast enough for use in programmable devices such as FPGAs process multiple packets with the words that were contained within the packets out of order, and then combines processed words in the correct order. Data advance and data delay techniques can be used to combine processed words correctly. The invention can be used for encryption, decryption, or both. Respective words from each data packet in a plurality of data packets are processed substantially simultaneously. Those respective words are processed in a first cipher path to generate intermediate blocks, and the intermediate blocks are processed in a second cipher path. Timing of the intermediate blocks after output from the first cipher path can be adjusted if necessary.
摘要翻译：用于实现CSA的方法和电路足以在诸如FPGA之类的可编程设备中使用，处理多个分组，其中包含在分组中的单词不正确，然后以正确的顺序组合处理的单词。可以使用数据提前和数据延迟技术来正确地组合处理的单词。本发明可以用于加密，解密或两者。基本上同时处理来自多个数据分组中的每个数据分组的相应单词。在第一密码路径中处理这些各个字以产生中间块，并且在第二密码路径中处理中间块。如果需要，可以调整从第一密码路径输出之后的中间块的时序。

108. 发明授权

US08626815B1 Configuring a programmable integrated circuit device to perform matrix multiplication 有权
标题翻译：配置可编程集成电路设备执行矩阵乘法
公开(公告)号：US08626815B1
公开(公告)日：2014-01-07
申请号：US12396739
申请日：2009-03-03
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F17/14 , G06F7/38 , G06F7/32 , G06F7/52
CPC分类号： G06F17/16
摘要： In a matrix multiplication in which each element of the resultant matrix is the dot product of a row of a first matrix and a column of a second matrix, each row and column can be broken into manageable blocks, with each block loaded in turn to compute a smaller dot product, and then the results can be added together to obtain the desired row-column dot product. The earliest results for each dot product are saved for a number of clock cycles equal to the number of portions into which each row or column is divided. The results are then added to provide an element of the resultant matrix. To avoid repeated loading and unloading of the same data, all multiplications involving a particular row-block can be performed upon loading that row-block, with the results cached until other multiplications for the resultant elements that use the cached results are complete.
摘要翻译：在矩阵乘法中，其中所得矩阵的每个元素是第一矩阵的行和第二矩阵的列的点积，每行和列可以被分解成可管理的块，每个块依次加载以计算较小的点积，然后将结果加在一起以获得所需的行列点积。每个点积的最早结果被保存多个时钟周期，等于每行或每列被划分的部分数量。然后加入结果以提供所得矩阵的元素。为了避免重复加载和卸载相同的数据，涉及特定行块的所有乘法可以在加载该行块时执行，结果缓存，直到使用缓存结果的结果元素的其他乘法完成。

109. 发明授权

US08620980B1 Programmable device with specialized multiplier blocks 有权
标题翻译：具有专用倍增器块的可编程器件
公开(公告)号：US08620980B1
公开(公告)日：2013-12-31
申请号：US12693614
申请日：2010-01-26
申请人： Volker Mauer , Martin Langhammer
发明人： Volker Mauer , Martin Langhammer
IPC分类号： G06F17/10
CPC分类号： H03H17/0294 , H03H17/0292 , H03H2218/10
摘要： A specialized multiplier block in a programmable device incorporates multipliers and adders, and is configurable as one or more types of finite impulse response (FIR) filter including a Direct Form II FIR filter. The specialized multiplier block further includes input and output registers to allow chaining of Direct Form II FIR filters into longer Direct Form II FIR filters. An output accumulator also allows the specialized multiplier block to operate as a time-division multiplexed FIR filter, performing several filtering operations during each clock cycle of the programmable device.
摘要翻译：可编程设备中的专用乘法器块包括乘法器和加法器，并且可配置为包括直接形式II FIR滤波器的一种或多种类型的有限脉冲响应（FIR）滤波器。专门的乘法器块还包括输入和输出寄存器，以允许直接形式II FIR滤波器链接到更长的直接形式II FIR滤波器中。输出累加器还允许专用乘法器块作为时分复用FIR滤波器工作，在可编程器件的每个时钟周期期间执行多个滤波操作。

110. 发明授权

US08549055B2 Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry 有权
标题翻译：模块化数字信号处理电路，具有电路模块之间任意可用的专用连接
公开(公告)号：US08549055B2
公开(公告)日：2013-10-01
申请号：US12716878
申请日：2010-03-03
申请人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F7/38 , G06F7/00
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

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