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    • 104. 发明授权
    • Respiration-synchronized oxygen supplying apparatus
    • 呼吸同步供氧装置
    • US06347630B1
    • 2002-02-19
    • US09294353
    • 1999-04-20
    • Masao TakahashiMasaji Otake
    • Masao TakahashiMasaji Otake
    • A61M1600
    • A61M16/0858A61M16/022A61M16/0677A61M2016/0021
    • A respiration-synchronized oxygen supplying apparatus includes a sensor detecting respiration of human being, a valve connecting and disconnecting communications between a first gas passage coupled to the human being and a second gas passage coupled to the oxygen supplier, and a controller for controlling the valve based on information from the sensor. A negative pressure generating mechanism is provided having a communication area widened as closer to the human being between the valve and the human being, and a third gas passage is coupled to the negative pressure generating mechanism to normally communicate between the sensor and the human being. During an oxygen supplying state, oxygen does not leak toward the negative pressure sensor, so that the oxygen can be employed without waste.
    • 呼吸同步供氧装置包括检测人的呼吸的传感器,连接和连接到人的第一气体通道与连接到氧气供应器的第二气体通道之间的连通和断开连接的阀,以及用于控制阀 基于来自传感器的信息。 提供了一种负压产生机构,其具有在阀和人之间更接近人的通信区域,并且第三气体通道联接到负压产生机构以在传感器和人之间正常连通。 在供氧状态下,氧气不向负压传感器泄漏,因此氧气可以无浪费地使用。
    • 108. 发明授权
    • Error-correcting system
    • 纠错系统
    • US4394763A
    • 1983-07-19
    • US261181
    • 1981-04-24
    • Genzo NaganoMasao Takahashi
    • Genzo NaganoMasao Takahashi
    • G06F11/08G06F11/10G06F11/16G06F12/16G11C29/00
    • G11C29/70G06F11/1024
    • An error-correcting system is disclosed, which is located between a main memory and a central processing unit. The system includes a relief bit memory, an ECC or Error Correction Code logic circuit, a switching circuit and a correction controlling circuit. The ECC logic circuit detects the occurrence of a soft error and a hard error. When a hard error occurs in the memory, the defective memory cell thereof is switched to the relief bit memory. Accordingly, data to be written into the main memory or the relief bit memory is switched by means of the switching circuit. Similarly, data to be read from the main memory or the relief bit memory is also switched by the switching circuit. The data to be stored in the relief bit memory is validated by means of the ECC logic circuit and the switching circuit. Further, the (n+1)-bit soft and hard errors are reduced to n-bit soft and hard errors by means of the ECC logic circuit and the switching circuit.
    • PCT No.PCT / JP80 / 00199 Sec。 371日期:1981年5月1日 102(e)日期1981年4月24日PCT提交1980年8月29日PCT公布。 出版物WO81 / 00641 日期:1981年3月5日。公开了一种位于主存储器和中央处理单元之间的纠错系统。 该系统包括浮点位存储器,ECC或纠错码逻辑电路,开关电路和校正控制电路。 ECC逻辑电路检测到软错误和硬错误的发生。 当存储器发生硬错误时,其有缺陷的存储单元被切换到浮点位存储器。 因此,通过开关电路来切换要写入主存储器或浮点位存储器的数据。 类似地,由主存储器或浮点位存储器读取的数据也由切换电路切换。 存储在浮点位存储器中的数据通过ECC逻辑电路和开关电路来验证。 此外,通过ECC逻辑电路和开关电路将(n + 1)位的软和硬错误减少到n位软和硬错误。