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101. 发明授权

US07345314B2 Organic light emitting diode display and manufacturing method thereof 失效
标题翻译：有机发光二极管显示及其制造方法
公开(公告)号：US07345314B2
公开(公告)日：2008-03-18
申请号：US11202340
申请日：2005-08-11
申请人： Jae-Hoon Chung , Nam-Deog Kim , Jung-Soo Rhee , Beohm-Rock Choi , Jong-Sun Lim , Chang-Oh Jeong
发明人： Jae-Hoon Chung , Nam-Deog Kim , Jung-Soo Rhee , Beohm-Rock Choi , Jong-Sun Lim , Chang-Oh Jeong
IPC分类号： H01L27/15 , H01L29/161 , H01L31/12 , H01L31/153 , H01L33/00
CPC分类号： H01L27/12 , H01L27/3246 , H01L51/5218 , H01L51/5221 , H01L2227/323
摘要： An organic light emitting diode display includes an insulating layer, a stress buffer disposed on the insulating layer, a first electrode disposed on the stress buffer, an organic light emitting member disposed on the first electrode, and a second electrode disposed on the organic light emitting member.
摘要翻译：有机发光二极管显示器包括绝缘层，设置在绝缘层上的应力缓冲器，设置在应力缓冲器上的第一电极，设置在第一电极上的有机发光部件和设置在有机发光器件上的第二电极会员。

102. 发明申请

US20080017884A1 DISPLAY SUBSTRATE, DISPLAY APPARATUS HAVING THE DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE DISPLAY APPARATUS 审中-公开
标题翻译：显示基板，具有显示基板的显示装置及制造显示装置的方法
公开(公告)号：US20080017884A1
公开(公告)日：2008-01-24
申请号：US11766329
申请日：2007-06-21
申请人： Chang-Oh Jeong , Sang-Gab Kim , Jun-Hyung Souk , Hong-Gyun Kim , In-Sun Hwang , Min-Seok Oh , Hong-Kee Chin , Yu-Gwang Jeong , Seung-Ha Choi , Hi-Kuk Lee , Shi-Yul Kim
发明人： Chang-Oh Jeong , Sang-Gab Kim , Jun-Hyung Souk , Hong-Gyun Kim , In-Sun Hwang , Min-Seok Oh , Hong-Kee Chin , Yu-Gwang Jeong , Seung-Ha Choi , Hi-Kuk Lee , Shi-Yul Kim
IPC分类号： H01L27/13 , H01L21/3205 , H01L23/48
CPC分类号： G02F1/133528 , G02F1/134336 , G02F2001/133548 , H01L27/12
摘要： A display apparatus includes a first substrate, a gate line formed on the first substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line formed on the semiconductor layer and including a source electrode, a drain electrode facing the source electrode, a first electrode electrically connected to the drain electrode, in a second substrate facing the first substrate, a second electrode formed on the second substrate, and a liquid crystal layer disposed between the first electrode and the second electrode. At least one of the first and second electrodes includes a plurality of line patterns to polarize incident light.
摘要翻译：显示装置包括第一基板，形成在第一基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，形成在半导体层上的数据线，并且包括源极面对源电极的漏电极，与漏电极电连接的第一电极，与第一衬底相对的第二衬底，形成在第二衬底上的第二电极，以及设置在第一电极和第二电极之间的液晶层电极。第一和第二电极中的至少一个包括使入射光偏振的多个线图案。

103. 发明授权

US07304383B2 TFT substrate for liquid crystal display apparatus and method of manufacturing the same 失效
标题翻译：液晶显示装置用TFT基板及其制造方法
公开(公告)号：US07304383B2
公开(公告)日：2007-12-04
申请号：US10535304
申请日：2003-10-27
申请人： Beom-Seok Cho , Chang-Oh Jeong
发明人： Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/4908 , C22C9/00 , G02F1/133345 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/66765
摘要： There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate (10), a diffusion barrier layer (11) and a copper alloy layer (12) are formed on the TFT substrate, consecutively. The copper alloy includes a material from about 0.5 at % to about 15 at % to form a gate wiring layer. The material is used to form the diffusion barrier layer (11). A compound that comprises a material such as Zr, Ti, Hf, V, Ta, Ni, Cr, Nb, Co, Mn, Mo, W, Rh, Pd, Pt, etc. is deposited on the diffusion barrier layer (11) to a thickness from about 50 Å to about 5,000 Å. The deposited compound is then heat treated to convert the deposited compound into a silicide compound (11b). The transistor substrate has low resistance and high conductance. Also, etching process is simplified, and a mutual diffusion is prevented by means of the thin diffusion barrier layer.
摘要翻译：提供了一种用于LCD装置的TFT基板及其制造方法。连续地在TFT基板上形成基板（10），扩散阻挡层（11）和铜合金层（12）。铜合金包括约0.5at％至约15at％的材料以形成栅极布线层。该材料用于形成扩散阻挡层（11）。包含诸如Zr，Ti，Hf，V，Ta，Ni，Cr，Nb，Co，Mn，Mo，W，Rh，Pd，Pt等材料的化合物沉积在扩散阻挡层（11）上，至约50至约5000的厚度。然后将沉积的化合物进行热处理以将沉积的化合物转化为硅化物（11b）。晶体管衬底具有低电阻和高电导率。此外，简化了蚀刻工艺，并且通过薄的扩散阻挡层来防止相互扩散。

104. 发明申请

US20060163582A1 Thin film transistor substrate and method for forming metal wire thereof 有权
标题翻译：薄膜晶体管基板及其金属线形成方法
公开(公告)号：US20060163582A1
公开(公告)日：2006-07-27
申请号：US10539223
申请日：2003-03-26
申请人： Jae-Gab Lee , Chang-Oh Jeong , Myung-Mo Sung , Hee-Jung Yang , Beom-Seok Cho
发明人： Jae-Gab Lee , Chang-Oh Jeong , Myung-Mo Sung , Hee-Jung Yang , Beom-Seok Cho
IPC分类号： H01L29/76
CPC分类号： H01L29/78603 , G02F2001/136295 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/4908 , H01L2224/32245
摘要： The present invention relates to a thin film transistor substrate and a metal wiring method thereof, more particularly to a thin film transistor substrate comprising self-assembled monolayers between the substrate and the metal wiring, and a metal wiring method thereof. Since a thin film transistor substrate of the present invention comprises three-dimensionally cross-linked self-assembled monolayers between the Si surface and the metal wiring, it has good adhesion ability and anti-diffusion ability.
摘要翻译：薄膜晶体管基板及其金属布线方法技术领域本发明涉及薄膜晶体管基板及其金属布线方法，更具体地涉及在基板和金属布线之间包括自组装单层的薄膜晶体管基板及其金属布线方法。由于本发明的薄膜晶体管基板在Si表面和金属布线之间包含三维交联的自组装单层，因此具有良好的粘附能力和抗扩散能力。

105. 发明申请

US20060151788A1 Tft substrate for liquid crystal display apparatus and method of manufacturing the same 失效
标题翻译：用于液晶显示装置的Tft基板及其制造方法
公开(公告)号：US20060151788A1
公开(公告)日：2006-07-13
申请号：US10535304
申请日：2003-10-27
申请人： Beom-Seok Cho , Chang-Oh Jeong
发明人： Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： H01L29/4908 , C22C9/00 , G02F1/133345 , G02F1/136286 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/66765
摘要： There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate (10), a diffusion barrier layer (11) and a copper alloy layer (12) are formed on the TFT substrate, consecutively. The copper alloy includes a material from about 0.5 at % to about 15 at % to form a gate wiring layer. The material is used to form the diffusion barrier layer (11). A compound that comprises a material such as Zr, Ti, Hf, V, Ta, Ni, Cr, Nb, Co, Mn, Mo, W, Rh, Pd, Pt, etc. is deposited on the diffusion barrier layer (11) to a thickness from about 50 Å to about 5,000 Å. The deposited compound is then heat treated to convert the deposited compound into a silicide compound (11b). The transistor substrate has low resistance and high conductance. Also, etching process is simplified, and a mutual diffusion is prevented by means of the thin diffusion barrier layer.
摘要翻译：提供了一种用于LCD装置的TFT基板及其制造方法。连续地在TFT基板上形成基板（10），扩散阻挡层（11）和铜合金层（12）。铜合金包括约0.5at％至约15at％的材料以形成栅极布线层。该材料用于形成扩散阻挡层（11）。包含诸如Zr，Ti，Hf，V，Ta，Ni，Cr，Nb，Co，Mn，Mo，W，Rh，Pd，Pt等材料的化合物沉积在扩散阻挡层（11）上，至约50至约5000的厚度。然后将沉积的化合物进行热处理以将沉积的化合物转化为硅化物（11b）。晶体管衬底具有低电阻和高电导率。此外，简化了蚀刻工艺，并且通过薄的扩散阻挡层来防止相互扩散。

106. 发明申请

US20060011912A1 Method of forming a metal pattern and a method of fabricating tft array panel by using the same 审中-公开
标题翻译：形成金属图案的方法和使用该方法制造tft阵列面板的方法
公开(公告)号：US20060011912A1
公开(公告)日：2006-01-19
申请号：US10516602
申请日：2002-07-24
申请人： Hong-Sick Park , Sung-Chul Kang , Hong-Je Cho , An-Na Park , Pong-ok Park , Chang-Oh Jeong
发明人： Hong-Sick Park , Sung-Chul Kang , Hong-Je Cho , An-Na Park , Pong-ok Park , Chang-Oh Jeong
IPC分类号： H01L29/04
CPC分类号： H01L21/28008 , G03F7/0047 , H01L21/288 , H01L21/32051 , H01L27/12 , H01L27/124 , H01L29/66765 , H01L29/78669 , H01L51/0003 , H01L51/0015 , H01L51/0021 , H01L51/0545
摘要： With a metal pattern formation process and a method of manufacturing a thin film transistor array panel using the metal pattern formation process, an organometallic layer is formed by coating an organometallic complex containing metal. The organometallic layer is exposed to light through a photo mask, and developed to form a metal pattern.
摘要翻译：利用金属图案形成工艺和使用金属图案形成工艺制造薄膜晶体管阵列板的方法，通过涂覆含有金属的有机金属络合物形成有机金属层。有机金属层通过光掩模曝光，并显影形成金属图案。

107. 发明申请

US20050242401A1 Wire structure, a thin film transistor substrate of using the wire structure and a method of manufacturing the same 失效
标题翻译：线结构，使用线结构的薄膜晶体管基板及其制造方法
公开(公告)号：US20050242401A1
公开(公告)日：2005-11-03
申请号：US11170251
申请日：2005-06-29
申请人： Beom-Seok Cho , Chang-Oh Jeong
发明人： Beom-Seok Cho , Chang-Oh Jeong
IPC分类号： G02F1/1343 , G02F1/136 , G02F1/1362 , G02F1/1368 , G09F9/30 , H01L21/336 , H01L21/768 , H01L29/786 , H01L51/50 , H05B33/12 , H01L29/76
CPC分类号： G02F1/136227 , G02F1/136213 , G02F2001/13629
摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire include triple layers of an adhesion layer, a Ag containing layer and a protection layer. The adhesion layer includes one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta and Ta alloy, the Ag containing layer includes Ag or Ag alloy, and the protection layer includes one of IZO, Mo, Mo alloy, Cr and Cr alloy.
摘要翻译：薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。栅极绝缘层覆盖栅极线。在栅极绝缘层上形成半导体图形。在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。在数据线上形成保护层。在保护层上形成通过接触孔与漏电极连接的像素电极。栅极线和数据线包括粘合层，含Ag层和保护层的三层。粘合层包括Cr，Cr合金，Ti，Ti合金，Mo，Mo合金，Ta和Ta合金中的一种，含Ag层包括Ag或Ag合金，保护层包括IZO，Mo，Mo合金， Cr和Cr合金。

108. 发明授权

US06867108B2 Wiring line assembly and method for manufacturing the same, and thin film transistor array substrate having the wiring line assembly and method for manufacturing the same 有权
标题翻译：配线组装及其制造方法以及具有布线组件的薄膜晶体管阵列基板及其制造方法
公开(公告)号：US06867108B2
公开(公告)日：2005-03-15
申请号：US10112760
申请日：2002-04-02
申请人： Chang-Oh Jeong , Bong-Joo Kang , Jae-Gab Lee
发明人： Chang-Oh Jeong , Bong-Joo Kang , Jae-Gab Lee
IPC分类号： G02F1/1345 , G02F1/1362 , G02F1/1368 , G09F9/00 , G09F9/30 , H01L21/3205 , H01L21/336 , H01L21/77 , H01L21/84 , H01L23/52 , H01L23/532 , H01L27/12 , H01L29/43 , H01L29/49 , H01L29/786 , H01L21/20 , H01L29/04
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/13629 , G02F2001/136295 , H01L23/53242 , H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/4908 , H01L2924/0002 , H01L2924/00
摘要： In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer based on silicon nitride or an organic material is deposited onto the substrate, and patterned through dry etching such that the protective layer bears contact holes exposing the drain electrodes, the gate pads and the data pads, respectively. An indium zinc oxide or indium tin oxide-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, and subsidiary gate and data pads. The pixel electrodes are electrically connected to the drain electrodes, and the subsidiary gate and data pads to the gate and data pads.
摘要翻译：在制造薄膜晶体管阵列基板的方法中，玻璃基板进行氧等离子体处理。将银或银合金基导电层沉积到衬底上，并被图案化，从而形成在水平方向上进行的栅极线组件。栅极线组件包括栅极线，栅电极和栅极焊盘。此后，在衬底上沉积氮化硅基栅极绝缘层，并且在栅极绝缘层上依次形成半导体层和欧姆接触层。对半导体层和欧姆接触层进行HF处理。将银合金基导电层沉积到衬底上，并被图案化从而形成数据线组件。数据线组件包括跨越栅极线，源电极，漏电极和数据焊盘的数据线。基于氮化硅或有机材料的保护层沉积到衬底上，并通过干蚀刻图案化，使得保护层分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。将氧化铟锌或铟锡氧化物基层沉积在衬底上，并被图案化，从而形成像素电极，以及辅助栅极和数据焊盘。像素电极电连接到漏电极，辅助栅极和数据焊盘电连接到栅极和数据焊盘。

109. 发明授权

US06716660B2 Method for fabricating a wiring line assembly for a thin film transistor array panel substrate 失效
标题翻译：一种用于制造薄膜晶体管阵列面板基板的布线组件的方法
公开(公告)号：US06716660B2
公开(公告)日：2004-04-06
申请号：US10247727
申请日：2002-09-20
申请人： Chang-Oh Jeong , Jae-Gab Lee , Beom-Seok Cho
发明人： Chang-Oh Jeong , Jae-Gab Lee , Beom-Seok Cho
IPC分类号： H01L2100
CPC分类号： H01L27/124 , G02F1/136286 , H01L23/53242 , H01L23/53247 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： According to one aspect of the present invention, the thin film transistor array substrate basically includes a gate line assembly based on an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements and the alloy elements each bearing a low melting point. The gate line assembly comprises a gate electrode and a gate line. A data line assembly crosses over the gate line assembly while being insulated from the gate line assembly. The data line assembly comprises a source electrode, a drain electrode and a data line. A semiconductor layer contacts the source electrode and the drain electrode. The semiconductor layer forms a thin film transistor together with the gate electrode, the source electrode and the drain electrode. A pixel electrode is connected to the drain electrode.
摘要翻译：根据本发明的一个方面，薄膜晶体管阵列基板基本上包括基于Ag合金的栅极线组件。 Ag合金包含Ag和至少一种合金元素和各自具有低熔点的合金元素。栅极线组件包括栅电极和栅极线。数据线组件在与栅极线组件绝缘的同时跨过栅极线组件。数据线组件包括源电极，漏电极和数据线。半导体层接触源电极和漏电极。半导体层与栅电极，源电极和漏电极一起形成薄膜晶体管。像素电极连接到漏电极。

110. 发明授权

US06586286B2 Method for fabricating thin film transistor array substrate for liquid crystal display 有权
公开(公告)号：US06586286B2
公开(公告)日：2003-07-01
申请号：US10075584
申请日：2002-02-15
申请人： Woon-Yong Park , Jong-Soo Yoon , Chang-Oh Jeong
发明人： Woon-Yong Park , Jong-Soo Yoon , Chang-Oh Jeong
IPC分类号： H01L2904
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136222 , G02F2001/136231 , G02F2001/13629 , G02F2201/40 , H01L27/124 , H01L27/1288 , H01L29/458 , H01L29/4908
摘要： A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area. The passivation layer and the underlying layers are etched through the photoresist pattern to form a semiconductor pattern and contact windows. A pixel electrode, a supplemental gate pad and a supplemental data pad are then formed of indium tin oxide or indium zinc oxide. The gate and data line assemblies may be formed with a single layered structure. A black matrix and a color filter may be formed at the structured substrate before forming the pixel electrode, and an opening portion may be formed between the pixel electrode and the data line to prevent possible short circuits.

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