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101. 发明授权

US07133460B2 Apparatus and method for determining a data rate of packet data in a mobile communication system 有权
公开(公告)号：US07133460B2
公开(公告)日：2006-11-07
申请号：US09986216
申请日：2001-10-22
申请人： Sang-Min Bae , Young-Kwon Cho , Ho-Kyu Choi , Youn-Sun Kim , Jin-Woo Heo , Jong-Yoon Hwang , Hyun-Woo Lee , Sung-Jin Kim , Chu-Hyon Yi , Sun-Gi Ku , Hwan-Joon Kwon , Ju-Ho Lee
发明人： Sang-Min Bae , Young-Kwon Cho , Ho-Kyu Choi , Youn-Sun Kim , Jin-Woo Heo , Jong-Yoon Hwang , Hyun-Woo Lee , Sung-Jin Kim , Chu-Hyon Yi , Sun-Gi Ku , Hwan-Joon Kwon , Ju-Ho Lee
IPC分类号： H04L27/04 , H04B1/707
CPC分类号： H04B7/264 , H04B1/707 , H04B2201/70705
摘要： Disclosed is a mobile station for determining a data rate for a packet data service in a mobile communication system including a base station, and the mobile station being provided with a voice service and a packet data service from the base station. In the mobile station, a receiver receives orthogonal code allocation information indicating the number of orthogonal codes allocated for the packet data service, a measurer measures a CIR using a received pilot channel, and a controller determines a data rate corresponding to the measured CIR, controls the determined data rate based on the number of the allocated orthogonal codes, and determines a controlled data rate.

102. 发明授权

US07113496B2 Apparatus and method for assigning a common packet channel in a CDMA communication system 有权
标题翻译：用于在CDMA通信系统中分配公共分组信道的装置和方法
公开(公告)号：US07113496B2
公开(公告)日：2006-09-26
申请号：US09788980
申请日：2001-02-20
申请人： Chang-Hoi Koo , Sung-Ho Choi , Ki-Ho Jung , Hyun-Woo Lee , Ho-Kyu Choi , Kyou-Woong Kim , Sung-Oh Hwang , Seong-Ill Park , Hyun-Jung Mun
发明人： Chang-Hoi Koo , Sung-Ho Choi , Ki-Ho Jung , Hyun-Woo Lee , Ho-Kyu Choi , Kyou-Woong Kim , Sung-Oh Hwang , Seong-Ill Park , Hyun-Jung Mun
IPC分类号： H04B7/216
CPC分类号： H04B7/2628 , H04B7/2637 , H04J13/0044 , H04J13/0048 , H04W52/0216 , H04W52/0235 , H04W52/12 , H04W52/325 , H04W52/58 , H04W72/0406 , H04W74/006 , H04W74/0833 , H04W76/36 , Y02D70/1242 , Y02D70/1262 , Y02D70/24 , Y02D70/25 , Y02D70/449
摘要： Disclosed is a method for indicating an end of transmitting data frames in order to enable a UTRAN (UMTS (Universal Mobile Telecommunications System) Terrestrial Radio Access Network) to assign a common packet channel to another user equipment (UE) in a UE for a CDMA mobile communication system. The UE requests assignment of any one of a number of common packet channels assignable in the UTRAN; the UE is assigned a common packet channel by the UTRAN in response to the to request; the UE sequentially transmits the data frames and their associated control frames over the assigned common packet channel; and the UE transmits at least one control frame, in an appointed field of which a given bit pattern appointed with the UTRAN is registered, in order to inform the UTRAN of an end of data transmission upon completing data transmission through the data frames.
摘要翻译：公开了一种用于指示发送数据帧的结束的方法，以便能够使UTRAN（UMTS（通用移动电信系统）陆地无线电接入网络）向用于CDMA的UE中的另一用户设备（UE）分配公共分组信道移动通信系统。 UE请求分配在UTRAN中可分配的多个公共分组信道中的任何一个; 响应于请求，UTRAN由UTRAN分配公共分组信道; UE在分配的公共分组信道上顺序发送数据帧及其相关控制帧; 并且UE在其被注册了指定的给定位模式的指定字段中发送至少一个控制帧，以便在通过数据帧完成数据传输时通知UTRAN数据传输结束。

103. 发明授权

US07088700B2 Apparatus and method for coding/decoding TFCI bits in an asynchronous CDMA communication system 有权
标题翻译：在异步CDMA通信系统中对TFCI位进行编码/解码的装置和方法
公开(公告)号：US07088700B2
公开(公告)日：2006-08-08
申请号：US09974656
申请日：2001-10-09
申请人： Hyun-Woo Lee , Jae-Yoel Kim , Sung-Ho Choi , Kyeong-Cheol Yang
发明人： Hyun-Woo Lee , Jae-Yoel Kim , Sung-Ho Choi , Kyeong-Cheol Yang
IPC分类号： H04B7/216
CPC分类号： H04L1/0069 , H04B1/707 , H04L1/0009 , H04L1/0025 , H04L1/0039 , H04L1/0072 , H04L1/0091 , H04W48/08
摘要： Disclosed is an apparatus for encoding TFCI bits in an asynchronous CDMA mobile communication system including a UE and a Node B for transmitting packet data to the UE. A TFCI bit generator creates the TFCI bits, the number of which is variable depending on an information bit ratio of the first channel to the second channel. A code length information generator generates code length information for setting a length of a codeword according to the information bit ratio. A Walsh code generator generates first to fifth basis Walsh codewords. A sequence generator generates an all-1 sequence. A mask generator generates first to fourth basis masks. First to tenth multipliers multiply the TFCI bits by the first to fifth basis Walsh codewords, the all-1 sequence and the first to fourth basis masks, respectively. An adder adds outputs of the first to tenth multipliers. A puncturer punctures a codeword output from the adder according to the code length information.
摘要翻译：公开了一种用于编码包括UE和用于向UE发送分组数据的节点B的异步CDMA移动通信系统中的TFCI比特的装置。 TFCI位生成器创建TFCI位，其数量根据第一通道与第二通道的信息比特率而变化。码长信息生成器生成用于根据信息比特率设置码字的长度的码长信息。沃尔什码发生器产生第一到第五基准沃尔什码字。序列发生器生成一个全序列。掩模发生器产生第一至第四基准掩模。第一至第十乘法器将TFCI比特分别乘以第一至第五基准沃尔什码字，全序列和第一至第四基本掩码。加法器将第一至第十乘法器的输出相加。穿刺器根据码长度信息来刺穿从加法器输出的码字。

104. 发明授权

US07068638B2 Apparatus and method for coding/decoding TFCI bits in an asynchronous CDMA communication system 失效
公开(公告)号：US07068638B2
公开(公告)日：2006-06-27
申请号：US10085776
申请日：2002-02-27
申请人： Sung-Ho Choi , Jae-Yoel Kim , Hyun-Woo Lee
发明人： Sung-Ho Choi , Jae-Yoel Kim , Hyun-Woo Lee
IPC分类号： H04B7/216
CPC分类号： H04L1/0072 , H04B1/7075 , H04B2201/70703 , H04J13/0048 , H04J13/12
摘要： A method for decoding received data in a decoder which receives data from an encoder varying a length of a Walsh code according to a coding rate of transmission data, and has maximum IFHT (Inverse Fast Hadamard Transform) stages capable of decoding even the data encoded by a Walsh code with a maximum length. The method comprises selecting at least one IFHT stage among the maximum IFHT stages according to a length of the Walsh code used for the received data; and performing inverse fast Hadamard transform on the received data by the selected IFHT stage.

105. 发明申请

US20060132203A1 Delay locked loop for use in semiconductor memory device and method thereof 有权
标题翻译：延迟锁定环用于半导体存储器件及其方法
公开(公告)号：US20060132203A1
公开(公告)日：2006-06-22
申请号：US11144474
申请日：2005-06-02
申请人： Hyun-Woo Lee
发明人： Hyun-Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/089
摘要： A delay locked loop (DLL) for generating a delay locked clock signal includes a delay line unit for delaying an external clock signal according to a delay amount control signal to thereby generate the delay locked clock signal; a divider for dividing the delay locked clock signal by a predetermined number determined based on a column address strobe (CAS) latency to thereby generate a divided signal; and a delay line control unit for generating the delay amount control signal based on a result of comparing a phase of the external clock signal and a delayed signal of the divided signal.
摘要翻译：用于产生延迟锁定时钟信号的延迟锁定环（DLL）包括延迟线单元，用于根据延迟量控制信号延迟外部时钟信号，从而产生延迟锁定时钟信号; 分频器，用于将延迟锁定时钟信号除以基于列地址选通（CAS）等待时间确定的预定数量，从而产生分频信号; 以及延迟线控制单元，用于基于将外部时钟信号的相位与分频信号的延迟信号进行比较的结果来产生延迟量控制信号。

106. 发明授权

US07010317B2 Apparatus and method for transmitting TFCI used for DSCH in a W-CDMA mobile communication system 失效
公开(公告)号：US07010317B2
公开(公告)日：2006-03-07
申请号：US10039332
申请日：2001-11-07
申请人： Sung-Oh Hwang , Kook-Heui Lee , Hyun-Woo Lee , Sung-Ho Choi , Byung-Jae Kwak , Yang-Hee Suh
发明人： Sung-Oh Hwang , Kook-Heui Lee , Hyun-Woo Lee , Sung-Ho Choi , Byung-Jae Kwak , Yang-Hee Suh
IPC分类号： H04Q7/20
CPC分类号： H04W52/40 , H04W52/16 , H04W52/54
摘要： Disclosed is a method for determining transmission power of a second TFCI bit indicating transport format information of data on a downlink shared channel transmitted from a selected Node B to a UE in a mobile communication system including the UE existing in a handover zone and a plurality of Node Bs in an active set of the UE. The Node Bs transmit dedicated channel data including a first TFCI bit to the UE over dedicated channels. A first Node B transmits dedicated channel data over a dedicated channel and transmits downlink shared channel data over the downlink shared channel. The first Node B determines a transmission power level of the second TFCI bit to be higher than a ratio of transmission power of the dedicated channel data from a Node B transmitting only the dedicated channel data to transmission power of the first TFCI bit.

107. 发明授权

US07006482B1 Apparatus and method for gating data on a control channel in a CDMA communication system 有权
标题翻译：用于在CDMA通信系统中的控制信道上门控数据的装置和方法
公开(公告)号：US07006482B1
公开(公告)日：2006-02-28
申请号：US09677342
申请日：2000-10-02
申请人： Ho-Kyu Choi , Chang-Soo Park , Sung-Oh Hwang , Hyun-Woo Lee , Jae-Min Ahn , Youn-Sun Kim , Hi-Chan Moon , Seong-ill Park
发明人： Ho-Kyu Choi , Chang-Soo Park , Sung-Oh Hwang , Hyun-Woo Lee , Jae-Min Ahn , Youn-Sun Kim , Hi-Chan Moon , Seong-ill Park
IPC分类号： H04B7/216
CPC分类号： H04W52/56 , H04B2201/70709 , H04J13/00 , H04W52/16 , H04W52/44 , H04W52/58
摘要： A method for transmitting control data on a downlink and/or uplink channel in a base station and/or mobile station in a mobile communication system. In one embodiment, the base station determines whether there is downlink channel data to transmit to a mobile station. If there is no data to be transmitted over the downlink channel for a predetermined time period, the base station drives a random gating position selector to determine a random gating slot position, gates on the control data at the determined slot position, and gates off the control data at other slot positions. The random position selector determines the gating slot position by calculating a value x by multiplying a system frame number (SFN) of a received signal by a specific integer; selecting n bits starting from a position which is at an x-chip distance from the start point of a scrambling code, which has a period equal to one frame, before a plurality of gating durations used in generating a downlink signal; and determining a gating slot position of a corresponding gating slot group by performing a modulo operation on the selected n bits, where the module operation is by the number of slots in a gating slot group.
摘要翻译：一种用于在移动通信系统中的基站和/或移动台中的下行链路和/或上行链路信道上发送控制数据的方法。在一个实施例中，基站确定是否存在要向移动台发送的下行链路信道数据。如果在预定时间段内没有要通过下行链路信道发送的数据，则基站驱动随机门控位置选择器以确定随机门控时隙位置，在所确定的时隙位置对控制数据进行门控，并关闭在其他插槽位置控制数据。随机位置选择器通过将接收信号的系统帧号（SFN）乘以特定整数来计算值x来确定选通时隙位置; 在用于生成下行链路信号的多个选通持续时间之前，从具有周期等于一帧的扰码开始点处的x码片距离的位置开始选择n个比特; 以及通过对所选择的n位执行模运算来确定对应的门控时隙组的门控时隙位置，其中模块操作是通过门控时隙组中的时隙数量。

108. 发明授权

US06961387B2 Apparatus and method for coding/decoding optimal (11,5) codeword in a mobile communication system 有权
标题翻译：用于在移动通信系统中编码/解码最优（11,5）码字的装置和方法
公开(公告)号：US06961387B2
公开(公告)日：2005-11-01
申请号：US09957967
申请日：2001-09-21
申请人： Jae-Yoel Kim , Hyun-Woo Lee , Kook-Heui Lee
发明人： Jae-Yoel Kim , Hyun-Woo Lee , Kook-Heui Lee
IPC分类号： H04J11/00 , H04L1/00 , H04L23/02 , H04L5/12
CPC分类号： H04L1/0057 , H04J13/004 , H04J13/12 , H04L1/0041 , H04L1/0045 , H04L1/0069 , H04L1/0072
摘要： An apparatus encodes an input information bit stream comprised of 5 bits into a (11,5) codeword comprised of 11 coded symbols. The apparatus comprises a Reed-Muller encoder for encoding the input information bit stream into a first order Reed-Muller codeword comprised of 16 coded symbols; and a puncturer for selecting a second coded symbol position or a third coded symbol position out of the 16 coded symbols constituting the first order Reed-Muller codeword, puncturing the coded symbols at intervals of 3 symbols beginning at the selected position, and thus outputting an optimal (11,5) codeword.
摘要翻译：一种装置将由5比特组成的输入信息比特流编码成由11个编码符号组成的（11,5）码字。该装置包括用于将输入信息比特流编码成由16个编码符号组成的一阶里德 - 穆勒码字的里德 - 穆勒编码器; 以及一个穿孔器，用于从构成一阶里德 - 穆勒码字的16个编码符号中选择第二编码符号位置或第三编码符号位置，以从所选择的位置开始的3个符号间隔进行穿孔，从而输出最优（11,5）码字。

109. 发明授权

US06956948B1 Apparatus and method for generating multiple scrambling codes in asynchronous mobile communication system 失效
标题翻译：在异步移动通信系统中生成多个扰码的装置和方法
公开(公告)号：US06956948B1
公开(公告)日：2005-10-18
申请号：US09667350
申请日：2000-09-22
申请人： Sung-Oh Hwang , Hee-Won Kang , Hyun-Woo Lee
发明人： Sung-Oh Hwang , Hee-Won Kang , Hyun-Woo Lee
IPC分类号： H03K3/84 , H04B1/707 , H04B7/26 , H04J11/00 , H04J13/10 , H04L7/00 , H04W4/00 , H04W16/14 , G06F17/00
CPC分类号： H04J13/12 , H04B1/707 , H04B2201/70703 , H04J13/0044 , H04J2013/0037
摘要： An apparatus and method for generating multiple scrambling codes in an asynchronous mobile communication system. In a scrambling code generating apparatus for generating a current scrambling code and a compressed mode scrambling code for compressed mode transmission in a base station device having a spreader for spreading an input data sequence with one of a plurality of OVSF codes and a scrambler for scrambling the spread data sequence with a primary scrambling code used as a default or one of a plurality of secondary scrambling codes according to the number of mobile stations in communication, a first feedback linear shift register generates an m-sequence from first predetermined initial bits, a second feedback linear shift register generates another m-sequence from second predetermined initial bits, a first adder generates the current scrambling code by adding the outputs of the first and second linear feedback shift registers, a second adder adds the output of the second linear feedback register and an m-sequence one bit delayed from the output of the first linear feedback register, and a third adder adds the output of the second linear feedback register and an m-sequence two bits delayed from the output of the first linear feedback register. Here, the compressed mode scrambling code is one of the outputs of the second and third adders and provided to the scrambler to scramble the spread data sequence.
摘要翻译：一种用于在异步移动通信系统中产生多个扰码的装置和方法。在用于产生用于压缩模式传输的当前扰码的扰码产生装置和具有用于使用多个OVSF码中的一个扩展输入数据序列的扩展器的基站装置和用于扰频所述加扰器的加扰器的压缩模式扰码第一反馈线性移位寄存器根据第一预定初始位产生m序列，第二预定初始位产生m序列，第二反向线性移位寄存器根据在通信中的移动站的数量，反馈线性移位寄存器从第二预定初始位产生另一个m序列，第一加法器通过将第一和第二线性反馈移位寄存器的输出相加来产生当前扰码，第二加法器将第二线性反馈寄存器的输出和从第一线性反馈寄存器的输出延迟一位的m序列，以及thi 第r个加法器将第二个线性反馈寄存器的输出和从第一个线性反馈寄存器的输出延迟的m序列两位相加。这里，压缩模式扰频码是第二和第三加法器的输出之一，并且提供给加扰器以加扰扩展数据序列。

110. 发明授权

US06943602B1 Delay locked loop and locking method thereof 有权
标题翻译：延迟锁定环及其锁定方法
公开(公告)号：US06943602B1
公开(公告)日：2005-09-13
申请号：US11026970
申请日：2004-12-30
申请人： Hyun-Woo Lee
发明人： Hyun-Woo Lee
IPC分类号： G06F1/10 , G11C11/407 , G11C11/4076 , H03K5/13 , H03L7/06 , H03L7/081 , H03L7/089
CPC分类号： H03L7/0814 , H03L7/089
摘要： The present invention provides a delay locked loop of a semiconductor memory device for preventing a stuck fail. The DLL of the present invention includes: a buffer for outputting a first clock corresponding to an in-phase of an external clock and outputting a second clock corresponding to an out-of-phase of the external clock; a phase comparator for outputting a control signal to increase/decrease a delay amount after comparing the first clock with a phase of a feedback clock; a shift register for outputting a shift signal in accordance with the control signal; a multiplexing unit for selecting one between the first and the second clocks by using the output of the phase comparator and the output of the shift register.
摘要翻译：本发明提供一种用于防止卡住失败的半导体存储器件的延迟锁定环。本发明的DLL包括：缓冲器，用于输出对应于外部时钟的同相的第一时钟并输出与外部时钟的异相相对应的第二时钟; 相位比较器，用于在将第一时钟与反馈时钟的相位进行比较之后输出用于增加/减少延迟量的控制信号; 移位寄存器，用于根据控制信号输出移位信号; 复用单元，用于通过使用相位比较器的输出和移位寄存器的输出来选择第一和第二时钟之间的一个。

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