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101. 发明授权

US07042967B2 Reduced complexity sliding window based equalizer 失效
标题翻译：降低复杂性滑动窗口均衡器
公开(公告)号：US07042967B2
公开(公告)日：2006-05-09
申请号：US10875900
申请日：2004-06-24
申请人： Alexander Reznik , Rui Yang , Bin Li , Ariela Zeira
发明人： Alexander Reznik , Rui Yang , Bin Li , Ariela Zeira
IPC分类号： H03D1/04 , H03D1/06 , H03K5/01 , H03K6/04 , H04B1/10
CPC分类号： H04L25/0242 , H04B1/71052 , H04L25/0212 , H04L25/03057 , H04L25/03292 , H04L2025/03426 , H04L2025/03509 , H04L2025/03605
摘要： The present invention has many aspects. One aspect of the invention is to perform equalization using a sliding window approach. A second aspect reuses information derived for each window for use by a subsequent window. A third aspect utilizes a discrete Fourier transform based approach for the equalization. A fourth aspect relates to handling oversampling of the received signals and channel responses. A fifth aspect relates to handling multiple reception antennas. A sixth embodiment relates to handling both oversampling and multiple reception antennas.
摘要翻译：本发明具有许多方面。本发明的一个方面是使用滑动窗口方法进行均衡。第二个方面重用为每个窗口导出的信息，供后续窗口使用。第三方面利用基于离散傅立叶变换的均衡方法。第四方面涉及处理接收信号和信道响应的过采样。第五方面涉及处理多个接收天线。第六实施例涉及处理过采样和多个接收天线。

102. 发明授权

US07010070B2 High performance wireless receiver with cluster multipath interference suppression circuit 失效
标题翻译：具有集群多径干扰抑制电路的高性能无线接收机
公开(公告)号：US07010070B2
公开(公告)日：2006-03-07
申请号：US10889939
申请日：2004-07-13
申请人： Bin Li , Rui Yang , Alexander Reznik , Ariela Zeira
发明人： Bin Li , Rui Yang , Alexander Reznik , Ariela Zeira
IPC分类号： H04B1/10 , H04B7/216
CPC分类号： H04B1/7113 , H04B1/7115 , H04L25/03038 , H04L25/03987 , H04L2025/03592
摘要： A receiver which suppresses inter-cluster multipath interference by processing an impulse channel response consisting of two multipath clusters, each cluster having groups of signals with multiple delays. In one embodiment, the receiver includes a single antenna and parallel-connected delay units used to align the groups of signals before being input into respective sliding window equalizers. The outputs of the equalizers are combined at chip level via a combiner which provides a single output. In another embodiment, a Cluster Multipath Interference Suppression (CMIS) circuit is incorporated into the receiver. The CMIS circuit includes a hard decision unit and a plurality of signal regeneration units to generate replicas of the multipath clusters. The replicas are subtracted from the respective outputs of the delay units and the results are input to the respective sliding window equalizers. In another embodiment, multiple antennas are used to receive and process the clusters.
摘要翻译：一种通过处理由两个多径簇组成的脉冲信道响应来抑制簇间多径干扰的接收机，每个簇具有多个延迟的信号组。在一个实施例中，接收机包括单个天线和并联连接的延迟单元，用于在输入到相应的滑动窗口均衡器之前将信号组对准。均衡器的输出通过提供单个输出的组合器在芯片级组合。在另一个实施例中，集群多路径干扰抑制（CMIS）电路并入接收机。 CMIS电路包括硬决策单元和多个信号再生单元以生成多路径簇的副本。从延迟单元的相应输出中减去副本，并将结果输入到各个滑动窗均衡器。在另一个实施例中，使用多个天线来接收和处理簇。

103. 发明申请

US20050063500A1 High performance wireless receiver with cluster multipath interference suppression circuit 失效
标题翻译：具有集群多径干扰抑制电路的高性能无线接收机
公开(公告)号：US20050063500A1
公开(公告)日：2005-03-24
申请号：US10889939
申请日：2004-07-13
申请人： Bin Li , Rui Yang , Alexander Reznik , Ariela Zeira
发明人： Bin Li , Rui Yang , Alexander Reznik , Ariela Zeira
IPC分类号： H04B1/7115 , H04B1/00 , H04L25/03 , H04Q20060101 , H04B1/10
CPC分类号： H04B1/7113 , H04B1/7115 , H04L25/03038 , H04L25/03987 , H04L2025/03592
摘要： A receiver which suppresses inter-cluster multipath interference by processing an impulse channel response consisting of two multipath clusters, each cluster having groups of signals with multiple delays. In one embodiment, the receiver includes a single antenna and parallel-connected delay units used to align the groups of signals before being input into respective sliding window equalizers. The outputs of the equalizers are combined at chip level via a combiner which provides a single output. In another embodiment, a Cluster Multipath Interference Suppression (CMIS) circuit is incorporated into the receiver. The CMIS circuit includes a hard decision unit and a plurality of signal regeneration units to generate replicas of the multipath clusters. The replicas are subtracted from the respective outputs of the delay units and the results are input to the respective sliding window equalizers. In another embodiment, multiple antennas are used to receive and process the clusters.
摘要翻译：一种通过处理由两个多径簇组成的脉冲信道响应来抑制簇间多径干扰的接收机，每个簇具有多个延迟的信号组。在一个实施例中，接收机包括单个天线和并联连接的延迟单元，用于在输入到相应的滑动窗口均衡器之前将信号组对准。均衡器的输出通过提供单个输出的组合器在芯片级组合。在另一个实施例中，集群多路径干扰抑制（CMIS）电路并入接收机。 CMIS电路包括硬决策单元和多个信号再生单元以生成多路径簇的副本。从延迟单元的相应输出中减去副本，并将结果输入到各个滑动窗均衡器。在另一个实施例中，使用多个天线来接收和处理簇。

104. 发明申请

US20050053167A1 Method for estimating signal magnitude, noise power, and signal-to-noise ratio of received signals 失效
标题翻译：用于估计接收信号的信号幅度，噪声功率和信噪比的方法
公开(公告)号：US20050053167A1
公开(公告)日：2005-03-10
申请号：US10750203
申请日：2003-12-31
申请人： Bin Li , Gregory Sternberg , Philip Pietraski
发明人： Bin Li , Gregory Sternberg , Philip Pietraski
IPC分类号： H04L1/20 , H04L27/38 , H04L5/12
CPC分类号： H04L27/38 , H04L1/20
摘要： An improved system and method for estimating one or more parameters, such as amplitude and signal-to-noise ratio, of a received signal, such as an M-QAM or q-ASK signal, is set forth herein. A first embodiment of the invention estimates the amplitude of an M-QAM signal based upon known or ascertainable phase information regarding a plurality of transmitted symbols. A respective set of received symbols corresponding to the plurality of transmitted symbols is recovered. Each of the plurality of received symbols is multiplied by a complex unit vector with a phase that is opposite in sign to the complex transmitted data symbol to generate a set of products. The set of products is summed, and the real part of the sum of products is then determined. The absolute values of the known transmitted symbols are summed to generate a total magnitude value. The real part of the sum of products is divided by the sum of transmitted magnitude values to generate an estimate of the amplitude of the M-QAM signal. Other embodiments of the present invention utilize second-order and fourth-order moments of received samples, a maximum likelihood searching process, or a Kurtosis estimation process to estimate amplitude, noise power, and signal-to-noise ratio of a received signal.
摘要翻译：本文阐述了用于估计接收信号（诸如M-QAM或q-ASK信号）的一个或多个参数（诸如振幅和信噪比）的改进的系统和方法。本发明的第一实施例基于关于多个发送符号的已知或可确定的相位信息估计M-QAM信号的幅度。恢复对应于多个发送符号的相应的一组接收符号。将多个接收到的符号中的每一个乘以具有与符号相反的相位的复数单位向量到复数发送的数据符号，以生成一组乘积。产品组合相加，然后确定产品总额的实际部分。已知发射符号的绝对值被相加以产生总幅值。将产品总和的实部除以发送的幅度值的和以产生M-QAM信号的幅度的估计。本发明的其它实施例利用接收样本的二阶和四阶矩，最大似然搜索处理或者一种用于估计接收信号的幅度，噪声功率和信噪比的一个峰值估计过程。

105. 发明申请

US20050031024A1 Reduced complexity sliding window based equalizer 失效
标题翻译：降低复杂性滑动窗口均衡器
公开(公告)号：US20050031024A1
公开(公告)日：2005-02-10
申请号：US10791244
申请日：2004-03-02
申请人： Rui Yang , Bin Li , Alexander Reznik , Ariela Zeira
发明人： Rui Yang , Bin Li , Alexander Reznik , Ariela Zeira
IPC分类号： H04B1/38 , H04L25/02 , H04L25/03
CPC分类号： H04L25/03057 , H04L25/0212 , H04L25/0242 , H04L25/03292 , H04L2025/03605
摘要： A sliding window based data estimation is performed. An error is introduced in the data estimation due to the communication model modeling the relationship between the transmitted and received signals. To compensate for an error in the estimated data, the data that was estimated in a previous sliding window step or terms that would otherwise be truncated as noise are used. These techniques allow for the data to be truncated prior to further processing reducing the data of the window.
摘要翻译：执行基于滑动窗口的数据估计。由于通信模型对发送和接收信号之间的关系建模，在数据估计中引入了误差。为了补偿估计数据中的错误，使用在先前的滑动窗口步骤中估计的数据或否则将被截断为噪声的术语。这些技术允许在进一步处理之前对数据进行截断以减少窗口的数据。

106. 发明授权

US06668011B1 Block detection receiver 有权
标题翻译：块检测接收机
公开(公告)号：US06668011B1
公开(公告)日：2003-12-23
申请号：US09335845
申请日：1999-06-18
申请人： Bin Li , Wen Tong
发明人： Bin Li , Wen Tong
IPC分类号： H04B1707
CPC分类号： H04B1/707
摘要： A method and block detection receiver for detecting codes carried in a received signal processed into blocks of values. The method includes the steps of arranging the blocks into non-overlapping sets of at least two blocks per set; and for each set, executing a code detection operation over combinations of values, each combination containing one value from each block in the set. A single- or dual-maxima metric generator may be used. Preferably, the number of combinations of values is restricted and the values in a combination are weighted. The block detection receiver executes a form of sequence estimator. Accordingly, performance of the receiver is close to that of coherent detection and is much better than that of the conventional receivers which do not consider more than one consecutive block.
摘要翻译：一种方法和块检测接收器，用于检测处理成块值的接收信号中承载的码。该方法包括以下步骤：将块布置成每组至少两个块的非重叠集合; 并且对于每个集合，对值的组合执行代码检测操作，每个组合包含来自集合中的每个块的一个值。可以使用单或双最大值度量发生器。优选地，值的组合数量被限制，并且组合中的值被加权。块检测接收机执行序列估计器的形式。因此，接收机的性能接近于相干检测的性能，并且比不考虑多于一个连续块的常规接收机的性能好得多。

107. 发明授权

US06453303B1 Automated analysis for financial assets 有权
标题翻译：金融资产自动分析
公开(公告)号：US06453303B1
公开(公告)日：2002-09-17
申请号：US09640107
申请日：2000-08-15
申请人： Bin Li
发明人： Bin Li
IPC分类号： G06F1760
CPC分类号： G06Q40/02 , G06Q40/06 , G06Q40/08
摘要： A system is provided for automatically generating and displaying market analysis related to financial assets whereby the analysis is provided for substantially all financial assets. The system includes a computer, database accessible by the computer and having stored thereon historical and real time data relating to a financial asset, and software executing on the computer for generating and displaying market analysis. The market analysis may, but not necessarily, include historical and real time data, a measure of liquidity and volatility of a financial asset, a measure of a financial asset's historical performance, an analysis of a financial asset's return in relation to its risk, and computed correlation coefficients and analysis of relationships between a financial asset and its market or market sectors.
摘要翻译：提供一个系统，用于自动生成和显示与金融资产相关的市场分析，为大部分金融资产提供分析。该系统包括计算机，由计算机访问的数据库，其上存储有与金融资产相关的历史和实时数据，以及在计算机上执行的用于生成和显示市场分析的软件。市场分析可能但不一定包括历史和实时数据，金融资产的流动性和波动性度量，金融资产历史表现的度量，金融资产的风险回报分析，以及计算相关系数和金融资产与其市场或市场部门之间关系的分析。

108. 发明授权

US06285580B1 Method and apparatus for hardening a static random access memory cell from single event upsets 有权
标题翻译：用于从单事件扰乱硬化静态随机存取存储器单元的方法和装置
公开(公告)号：US06285580B1
公开(公告)日：2001-09-04
申请号：US09441941
申请日：1999-11-17
申请人： Ho Gia Phan , Derwin Jallice , Bin Li , Joseph Hoffman
发明人： Ho Gia Phan , Derwin Jallice , Bin Li , Joseph Hoffman
IPC分类号： G11C1100
CPC分类号： G11C11/4125
摘要： A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.
摘要翻译：公开了一种用于静态随机存取存储器的单事件硬化存储单元。单事件硬化存储单元包括第一组交叉耦合晶体管，第二组交叉耦合晶体管和一组隔离晶体管。隔离晶体管的组合耦合到第一组交叉耦合晶体管，使得在交叉耦合晶体管和隔离晶体管之间形成两个反转路径。

109. 发明授权

US06282140B1 Multiplexor having a single event upset (SEU) immune data keeper circuit 有权
标题翻译：多路复用器具有单次事件不适（SEU）免疫数据保持电路
公开(公告)号：US06282140B1
公开(公告)日：2001-08-28
申请号：US09589732
申请日：2000-06-08
申请人： Ho Gia Phan , Bin Li
发明人： Ho Gia Phan , Bin Li
IPC分类号： G11C800
CPC分类号： G11C5/005 , G11C11/4125
摘要： A multiplexor having a single event upset (SEU) hardened data keeper circuit is disclosed. The multiplexor includes a precharge transistor, an isolation transistor, an invertor, and an SEU immune storage cell. Both the gate of the precharge transistor and the gate of the isolation transistor are connected to a clock signal. The SEU immune storage cell has a first access node and a second access node. The first access node is complementary to the second access node. The first access node is connected to the precharge transistor and the second access node is connected to the isolation transistor. The invertor is coupled between the precharge transistor and the isolation transistor.
摘要翻译：公开了具有单个事件镦锻（SEU）硬化数据保持器电路的多路复用器。多路复用器包括预充电晶体管，隔离晶体管，反相器和SEU免疫存储单元。预充电晶体管的栅极和隔离晶体管的栅极都连接到时钟信号。 SEU免疫存储单元具有第一接入节点和第二接入节点。第一接入节点与第二接入节点互补。第一接入节点连接到预充电晶体管，第二接入节点连接到隔离晶体管。反相器耦合在预充电晶体管和隔离晶体管之间。

110. 发明授权

US06275080B1 Enhanced single event upset immune latch circuit 有权
标题翻译：增强单事件不安免疫锁定电路
公开(公告)号：US06275080B1
公开(公告)日：2001-08-14
申请号：US09480454
申请日：2000-01-11
申请人： Ho G. Phan , Derwin L. Jallice , Bin Li
发明人： Ho G. Phan , Derwin L. Jallice , Bin Li
IPC分类号： H03K3037
CPC分类号： H03K3/0375 , G11C5/005 , G11C11/4125
摘要： An enhanced single event upset immune CMOS latch circuit is formed of a first and a second cross-coupled invertor having isolation transistors in the path coupling the drains of the transistors in the first invertor.
摘要翻译：增强的单事件不安免疫CMOS锁存电路由第一和第二交叉耦合的反相器形成，其中第一和第二交叉耦合反相器在第一反相器中耦合晶体管的漏极的路径中具有隔离晶体管。

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