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101. 发明申请

US20080050879A1 METHODS OF FORMING METAL-CONTAINING GATE STRUCTURES 审中-公开
标题翻译：形成含金属结构结构的方法
公开(公告)号：US20080050879A1
公开(公告)日：2008-02-28
申请号：US11466656
申请日：2006-08-23
申请人： Cheng-Lung Hung , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
发明人： Cheng-Lung Hung , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/28079 , H01L21/28194 , H01L29/4958 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A method of forming a metal-containing gate includes forming a high-k dielectric layer over a substrate. A process using an oxygen-containing solution is provided to process the high-k dielectric layer. A metal-containing layer is formed over the high-k dielectric layer. The high-k dielectric layer and metal-containing layer are patterned, thereby defining a gate structure.
摘要翻译：形成含金属栅极的方法包括在衬底上形成高k电介质层。提供使用含氧溶液的方法来处理高k电介质层。在高k电介质层上形成含金属层。图案化高k电介质层和含金属层，由此限定栅极结构。

102. 发明申请

US20080001237A1 Semiconductor device having nitrided high-k gate dielectric and metal gate electrode and methods of forming same 审中-公开
标题翻译：具有氮化高k栅极电介质和金属栅电极的半导体器件及其形成方法
公开(公告)号：US20080001237A1
公开(公告)日：2008-01-03
申请号：US11478476
申请日：2006-06-29
申请人： Vincent S. Chang , Peng-Fu Hsu , Fong-Yu Yen , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Vincent S. Chang , Peng-Fu Hsu , Fong-Yu Yen , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L29/78
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28194 , H01L21/28202 , H01L21/823437 , H01L21/823462 , H01L21/823475 , H01L21/823828 , H01L21/823857 , H01L21/823871 , H01L29/4966 , H01L29/518 , H01L29/7833
摘要： Disclosed is a semiconductor device having a substrate, an interfacial layer formed on said substrate, a nitrogen-containing high dielectric constant (high-k) layer formed on said interfacial layer, and a metal electrode on said nitrogen-containing high-k layer. Also disclosed is a method of forming a transistor including forming on a substrate an interfacial layer comprising silicon and oxygen, depositing on the interfacial layer a high-k dielectric material, nitriding the high-k dielectric material, depositing a metal layer on the high-k dielectric material, and patterning the metal layer, the high-k dielectric material, and the interfacial layer to form a gate stack.
摘要翻译：公开了一种半导体器件，其具有基板，在所述基板上形成的界面层，在所述界面层上形成的含氮高介电常数（高k）层和所述含氮高k层上的金属电极。还公开了一种形成晶体管的方法，包括在衬底上形成包含硅和氧的界面层，在界面层上沉积高k电介质材料，氮化高k电介质材料，在高介电材料上沉积金属层， k电介质材料，并且图案化金属层，高k电介质材料和界面层以形成栅极堆叠。

103. 发明申请

US20070296002A1 Backside contacts for MOS devices 有权
标题翻译： MOS器件的背面触点
公开(公告)号：US20070296002A1
公开(公告)日：2007-12-27
申请号：US11475707
申请日：2006-06-27
申请人： Mong Song Liang , Hun-Jan Tao
发明人： Mong Song Liang , Hun-Jan Tao
IPC分类号： H01L29/76
CPC分类号： H01L29/78 , H01L21/76264 , H01L21/84 , H01L23/481 , H01L23/485 , H01L27/1203 , H01L29/41766 , H01L29/7843
摘要： A semiconductor structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate dielectric over the first surface of the semiconductor substrate, a gate electrode over the gate dielectric, a source/drain region having at least a portion in the semiconductor substrate, a dielectric layer having a first surface and a second surface opposite the first surface wherein the first surface of the dielectric layer adjoins the second surface of the semiconductor substrate, and a contact plug in the dielectric layer, wherein the contact plug extends from a bottom side of the source/drain region to the second surface of the dielectric layer.
摘要翻译：半导体结构包括具有第一表面和与第一表面相对的第二表面的半导体衬底，在半导体衬底的第一表面上的栅极电介质，栅极电介质上的栅电极，具有至少一部分的源/漏区在所述半导体衬底中，具有第一表面和与所述第一表面相对的第二表面的电介质层，其中所述电介质层的所述第一表面邻接所述半导体衬底的第二表面，以及所述电介质层中的接触插塞，其中所述接触插塞从源极/漏极区域的底部延伸到电介质层的第二表面。

104. 发明授权

US07276417B2 Hybrid STI stressor with selective re-oxidation anneal 有权
标题翻译：混合STI应力选择性再氧化退火
公开(公告)号：US07276417B2
公开(公告)日：2007-10-02
申请号：US11320221
申请日：2005-12-28
申请人： Kai-Ting Tseng , Yu-Lien Huang , Hao-Ming Lien , Ling-Yen Yeh , Hun-Jan Tao
发明人： Kai-Ting Tseng , Yu-Lien Huang , Hao-Ming Lien , Ling-Yen Yeh , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823807 , H01L29/7846
摘要： A method for forming stressors in a semiconductor substrate is provided. The method includes providing a semiconductor substrate including a first device region and a second device region, forming shallow trench isolation (STI) regions with a high-shrinkage dielectric material in the first and the second device regions wherein the STI regions define a first active region in the first device region and a second active region in the second device region, forming an insulation mask over the STI region and the first active region in the first device region wherein the insulation mask does not extend over the second device region, and performing a stress-tuning treatment to the semiconductor substrate. The first active region and second active region have tensile stress and compressive stress respectively. An NMOS and a PMOS device are formed on the first and second active regions, respectively.
摘要翻译：提供了一种在半导体衬底中形成应力源的方法。该方法包括提供包括第一器件区域和第二器件区域的半导体衬底，在第一和第二器件区域中形成具有高收缩介电材料的浅沟槽隔离（STI）区域，其中STI区域限定第一有源区域在所述第一器件区域和所述第二器件区域中的第二有源区域中，在所述STI区域和所述第一器件区域中的所述第一有源区域上形成绝缘掩模，其中所述绝缘掩模不在所述第二器件区域上延伸，并执行对半导体衬底进行应力调谐处理。第一活性区和第二活性区分别具有拉伸应力和压应力。分别在第一和第二有源区上形成NMOS和PMOS器件。

105. 发明授权

US07265060B2 Bi-level resist structure and fabrication method for contact holes on semiconductor substrates 有权
标题翻译：半导体衬底上的接触孔的双层抗蚀剂结构和制造方法
公开(公告)号：US07265060B2
公开(公告)日：2007-09-04
申请号：US10889416
申请日：2004-07-12
申请人： Ming Huan Tsai , Hun Jan Tao , Tsang Jiuh Wu , Ju Wang Hsu
发明人： Ming Huan Tsai , Hun Jan Tao , Tsang Jiuh Wu , Ju Wang Hsu
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3 or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2 or similar species, and a nitrogen source, such as N2, N2O, or NH3 or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.
摘要翻译：已经开发了一种通过介电层蚀刻非常小的接触孔的改进方法，其用于在半导体衬底上形成的多层集成电路中分离导电层。该方法在抗蚀剂结构中使用双层ARC涂层，并且在等离子体蚀刻工艺中使用气态组分的独特组合，其用于干燥显影双电平抗蚀剂掩模以及通过氧化硅介电层进行蚀刻。气体组分包括含氟气体的混合物，例如C 4 N 5 F 8 C 5 N 5 F 8 或类似物质，惰性气体，例如氦气或氩气，任选的弱氧化剂，例如氦气或氩气，等等。作为CO或O 2或类似物质，以及氮源，例如N 2，N 2 O或NH 3 或类似物种。图案化掩模层可用于可靠地蚀刻半导体衬底上的氧化硅层中的接触孔，其中孔的直径为约0.1微米或更小。

106. 发明申请

US20070111110A1 In-situ plasma treatment of advanced resists in fine pattern definition 有权
标题翻译：先进抗蚀剂的原位等离子体处理精细图案定义
公开(公告)号：US20070111110A1
公开(公告)日：2007-05-17
申请号：US11274109
申请日：2005-11-14
申请人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： G03F1/00 , C03C15/00 , G03C5/00
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.
摘要翻译：公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层，在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

107. 发明授权

US07141460B2 Method of forming trenches in a substrate by etching and trimming both hard mask and a photosensitive layers 有权
标题翻译：通过蚀刻和修整硬掩模和感光层来在衬底中形成沟槽的方法
公开(公告)号：US07141460B2
公开(公告)日：2006-11-28
申请号：US10899927
申请日：2004-07-27
申请人： Ming-Jie Huang , Hun-Jan Tao
发明人： Ming-Jie Huang , Hun-Jan Tao
IPC分类号： H01L21/00 , H01L21/84 , H01L21/3205 , H01L21/4763 , H01L21/302
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31116 , H01L21/32139 , Y10S430/151
摘要： A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anisotropically transferred through the ARC and hardmask. Then an isotropic etch to trim the linewidth by 0 to 50 nm per edge is performed simultaneously on the photoresist, ARC and hardmask. This method minimizes the amount of line end shortening to less than three times the dimension trimmed from one line edge. Since a majority of the photoresist layer is retained, the starting photoresist thickness can be reduced by 1000 Angstroms or more to increase process window. The pattern is then etched through the underlying layer to form a gate electrode. The method can also be used to form STI features in a substrate.
摘要翻译：描述了将光致抗蚀剂图案转印到基底中的方法。在一个实施例中，在栅极电极层上形成由顶部光致抗蚀剂层，中间ARC层和底部硬掩模构成的堆叠。光刻胶图案中的一条线通过ARC和硬掩模各向异性传输。然后，在光致抗蚀剂，ARC和硬掩模上同时进行各向同性蚀刻，以将每条边缘的线宽修剪0至50nm。该方法将线端缩短的量最小化为小于从一条线边缘修剪的尺寸的三倍。由于保留了光致抗蚀剂层的大部分，所以起始光致抗蚀剂的厚度可以减小1000埃以上，以增加工艺窗口。然后通过下面的层蚀刻图案以形成栅电极。该方法也可用于在基底中形成STI特征。

108. 发明申请

US20060220653A1 Measuring low dielectric constant film properties during processing 有权
标题翻译：在加工期间测量低介电常数膜性能
公开(公告)号：US20060220653A1
公开(公告)日：2006-10-05
申请号：US11096049
申请日：2005-03-31
申请人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
发明人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
IPC分类号： G01R31/00 , G01N21/00 , G01J4/00
CPC分类号： G01N21/211
摘要： A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.
摘要翻译：用于确定制造基板上的低k电介质膜的介电常数的方法和系统包括使用椭偏仪测量介电常数的电子部件，使用IR光谱仪测量介电常数的离子分量，测量总电介质使用微波光谱仪恒定并导出介电常数的偶极分量。测量和确定是非接触的，并且可以在进行测量后进一步处理的生产设备上进行。

109. 发明申请

US20060151430A1 Method and system for processing multi-layer films 有权
标题翻译：多层膜加工方法及系统
公开(公告)号：US20060151430A1
公开(公告)日：2006-07-13
申请号：US11358393
申请日：2006-02-21
申请人： Hui Yang , Miao-Ju Hsu , Chao-Cheng Chen , Hun-Jan Tao
发明人： Hui Yang , Miao-Ju Hsu , Chao-Cheng Chen , Hun-Jan Tao
IPC分类号： G01L21/30 , G01R31/00
CPC分类号： H01L21/31116 , H01J37/32935 , H01L22/26
摘要： A method of processing multi-layer films, the method including: (1) processing a plurality of layers according to selected parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the processing of the associated one of the plurality of layers, and (3) determining dynamic processing progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the processing.
摘要翻译：一种处理多层薄膜的方法，该方法包括：（1）根据选定的参数处理多个层，（2）确定多个光学特性，每个光学特性与多个层之一相关联，并在处理过程中确定所述多个层中的相关联的一个层，以及（3）基于与经历所述处理的所述多个层中的特定一个层相关联的所述多个光学特性中的一个来确定动态处理进度。

110. 发明授权

US07060628B2 Method for fabricating a hard mask polysilicon gate 有权
标题翻译：硬掩模多晶硅栅极的制造方法
公开(公告)号：US07060628B2
公开(公告)日：2006-06-13
申请号：US10804449
申请日：2004-03-19
申请人： Ming-Jie Huang , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Ming-Jie Huang , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A method for forming a patterned silicon-containing layer is disclosed. The method includes providing a substrate, providing a polysilicon layer on the substrate, providing a hard mask layer on the polysilicon layer, patterning and etching the hard mask layer and etching the polysilicon layer according to the pattern of the hard mask layer using a fluorine-containing etchant gas. The resulting sidewall profile of the etched polysilicon layer is substantially straight, uniform and devoid of a necking or notched configuration.
摘要翻译：公开了一种用于形成图案化的含硅层的方法。该方法包括提供衬底，在衬底上提供多晶硅层，在多晶硅层上提供硬掩模层，图案化和蚀刻硬掩模层，并根据硬掩模层的图案使用氟 - 含有蚀刻剂气体。蚀刻的多晶硅层的所得到的侧壁轮廓基本上是直的，均匀的且没有颈缩或缺口构型。

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