专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20210011081A1 CIRCUIT ARRANGEMENT COMPRISING A MICROPROCESSOR AND A VOLTAGE GENERATING CIRCUIT 有权
公开(公告)号：US20210011081A1
公开(公告)日：2021-01-14
申请号：US16846699
申请日：2020-04-13
申请人： Vitesco Technologies GMBH
发明人： Andreas Wunderlich , Alfons Fisch , Bernhard Bieg
IPC分类号： G01R31/3167 , H03M1/12 , H03M1/10
摘要： A circuit arrangement includes a microcontroller having a first analog-to-digital converter whose input is connected to the output of a first multiplexer whose output is connected to a first comparison device for comparing reference voltages, and a first serial interface circuit connected to the first comparison device. A voltage generating circuit includes a second analog-to-digital converter whose input is connected to the output of a second multiplexer whose output is connected to a number of registers, which are connected to a safety value generator and store digital values together with a respective safety value, and a second serial interface circuit connected to the registers. The first and second serial interface circuits are connected to each other for communication of the microcontroller with the voltage generating circuit, the first interface circuit being connected to a second comparison device for comparing supply voltages and/or currents with desired voltages and/or desired currents.

92. 发明授权

US10698027B1 Blended analog-to-digital conversion for digital test and measurement devices 有权
公开(公告)号：US10698027B1
公开(公告)日：2020-06-30
申请号：US16685157
申请日：2019-11-15
申请人： Liquid Instruments Pty Ltd.
发明人： Daniel Anthony Shaddock , Danielle Marie Rawles Wuchenich , Paul Anthony Altin , Timothy Tien-Yue Lam , Max Andrew Gordon Schwenke , Benjamin Paul Coughlan , David Sebastiaan Rabeling
IPC分类号： H03M1/10 , G01R31/3167 , H03M1/12
摘要： Systems and methods are provided for blended analog-to-digital conversion for digital test and measurement devices. A first-frequency-domain circuit path is configured to generate a first processed digital signal having high fidelity to an analog signal over a first frequency domain. A second-frequency-domain circuit path is configured to generate a second processed digital signal having high fidelity to the analog signal over a second frequency domain. A blended digital signal is generated using the first processed digital signal and the second processed digital signal. The blended digital signal can have high fidelity to the analog signal over multiple frequency domains.

93. 发明申请

US20190072610A1 System and Method for Electric Current Leakage Detection in A Land Seismic System 审中-公开
公开(公告)号：US20190072610A1
公开(公告)日：2019-03-07
申请号：US16083512
申请日：2017-03-15
申请人： WESTERNGECO LLC
发明人： Kambiz Iranpour , Stefan Johansson , Hans Paulson
IPC分类号： G01R31/3167 , G01V1/22 , G01V1/28 , H01H9/16 , H03M1/10 , G01P15/08 , G01R27/20
摘要： Embodiments disclosed herein are directed towards systems and methods for electric current leakage detection in a land seismic system. Embodiments may include generating at least one test signal using a digital to analog converter “DAC” circuitry, wherein the DAC circuitry includes an output operatively connected to earth ground. Embodiments may further include alternately grounding a positive path to an analog to digital converter “ADC” circuitry during a first time window and a negative path to the analog to digital converter during a second time window while measuring an ADC signal. Embodiments may also include determining an average amplitude of the first time window and the second time window and determining a leakage resistance based upon, at least in part, the average amplitude of the first time window and the second time window.

94. 发明申请

US20190004110A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190004110A1
公开(公告)日：2019-01-03
申请号：US15970057
申请日：2018-05-03
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Takuya LEE , Tetsuya KOKUBUN , Yutaka NAKADAI , Kenji SHIOZAWA , Yoshihide NAKAMURA
IPC分类号： G01R31/3167 , G06F15/78 , G01R31/3187
摘要： According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.

95. 发明授权

US10103074B2 Method to improve analog fault coverage using test diodes 有权
公开(公告)号：US10103074B2
公开(公告)日：2018-10-16
申请号：US15073009
申请日：2016-03-17
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Ronny Vanhooren , Wim Dobbelaere , Vahap Baris Esen , Anthony B. G. Coyette , Georges G. E. Gielen
IPC分类号： G01R31/26 , H01L21/66 , H01L27/08 , H01L27/088 , G06F17/50 , G01R31/28 , G01R31/3167
摘要： Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode, each of the one or more diodes may be coupled with a voltage domain. One or more test pins may be coupled with one or more diodes. The test pins may be configured to be coupled to a tester. The one or more diodes may be positioned on one or more internal analog nodes to detect the presence of one or more analog faults. The one or more diodes may be configured to remain inactive during regular operation of the integrated circuit.

96. 发明授权

US09494651B2 Method for testing embedded systems 有权
标题翻译：嵌入式系统测试方法
公开(公告)号：US09494651B2
公开(公告)日：2016-11-15
申请号：US14592585
申请日：2015-01-08
申请人： Andrzej Wlodzimierz Nawrocki
发明人： Andrzej Wlodzimierz Nawrocki
IPC分类号： G01R31/28 , G01R31/3187 , G01R31/3185 , G01R31/3167 , H02M1/00 , G01N1/00
CPC分类号： G01R31/3187 , G01N1/00 , G01N2201/00 , G01R31/3167 , G01R31/318508 , H02M1/00
摘要： Functional diagnostic testing of an electronic circuit board assembly with one or more embedded channels to be tested includes steps of: (a) connecting a channel under test; (b) imposing a known digital or analog voltage, as appropriate for a channel under test, that is generated by a digital or analog output of the electronic circuit board assembly; and (c) comparing data read by the channel under test with the stored value of the imposed voltage and required tolerance to determine whether the channel under test is within specifications. Diagnostic test implemented by digital logic and software residing onboard the electronic circuit board assembly. Execution of software or firmware code segment controls the diagnostic test sequence. Signal switching is facilitated by digital and analog multiplexers.
摘要翻译：具有一个或多个要测试的嵌入式通道的电子电路板组件的功能诊断测试包括以下步骤：（a）连接被测通道; （b）施加由所述电子电路板组件的数字或模拟输出产生的适用于被测信道的已知数字或模拟电压; 和（c）将被测试通道读取的数据与所施加的电压的存储值和所需的容限进行比较，以确定被测信道是否在规范内。由数字逻辑和软件实现的诊断测试驻留在电子电路板组件上。执行软件或固件代码段来控制诊断测试顺序。数字和模拟多路复用器便于信号切换。

97. 发明授权

US09459317B2 Mixed mode integrated circuit, method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit 有权
标题翻译：混合模式集成电路，向混合模式集成电路的子电路提供可控测试时钟信号的方法以及在混合模式集成电路中检测导致违反电磁兼容性标准的电流路径的方法
公开(公告)号：US09459317B2
公开(公告)日：2016-10-04
申请号：US14607798
申请日：2015-01-28
申请人： Pascal Kamel Abouda , Celine Hounaïda Abouda , Patrice Besse
发明人： Pascal Kamel Abouda , Celine Hounaïda Abouda , Patrice Besse
IPC分类号： H04L7/00 , G01R31/317 , G01R31/3167
CPC分类号： G01R31/31727 , G01R31/3167
摘要： A mixed mode integrated circuit, a method of providing a controllable test clock signal to a sub-circuitry of the mixed-mode integrated circuit and a method of detecting current paths causing violations of electromagnetic compatibility standards in the mixed mode integrated circuit are provided. The mixed mode integrated circuit 100 comprises in addition to a clock network 110 an integrated test clock signal generator 140 to generate test clock signals that are provided via controllable multiplexers 150, 160 to an analog and digital sub-circuitry, respectively, of the mixed-mode integrated circuit. The test clock signals are generated on basis of an input test clock signal having a controllable frequency. The clock network generates clock signals for the sub-circuitries that are used by the sub-circuitries under normal operational conditions. The controllable multiplexers provide either the test clock signal to a specific sub-circuitry or a clock signal received from the clock network.
摘要翻译：一种混合模式集成电路，一种向混合模式集成电路的子电路提供可控测试时钟信号的方法，以及一种检测混合模式集成电路中导致违反电磁兼容性标准的电流路径的方法。混合模式集成电路100除了时钟网络110之外还包括集成测试时钟信号发生器140，以产生经由可控多路复用器150,160分别提供给模拟和数字子电路的测试时钟信号，模式集成电路。基于具有可控频率的输入测试时钟信号产生测试时钟信号。时钟网络为在正常操作条件下的子电路使用的子电路产生时钟信号。可控多路复用器将测试时钟信号提供给从时钟网络接收的特定子电路或时钟信号。

98. 发明授权

US09448280B2 Circuit test system and method using a wideband multi-tone test signal 有权
标题翻译：电路测试系统和方法采用宽带多音测试信号
公开(公告)号：US09448280B2
公开(公告)日：2016-09-20
申请号：US13407811
申请日：2012-02-29
申请人： Timothy M. Platt , Mustapha Slamani , Tian Xia
发明人： Timothy M. Platt , Mustapha Slamani , Tian Xia
IPC分类号： G06F19/00 , G01R31/3167 , G01R31/28
CPC分类号： G01R31/3167 , G01R31/2837
摘要： A testing system and method incorporate a test signal generator for generating a test signal with multiple tones uniformly distributed across a wideband having a specific bandwidth. This test signal is generated based on user-specified test signal parameter(s) (e.g., using an orthogonal frequency-division multiplexing (OFDM) spread spectrum technique) and processed (e.g., converted from digital to analog or shifted to a different wideband having the same bandwidth), as necessary, so that it is suitable for application to a specific device under test and so that the tones account for the full range of frequencies with the wideband operation of that device under test. After it is applied to the device under test, the resulting output signal is captured, processed (e.g., converted back to digital or shifted back to the initial wideband), as necessary, and analyzed in order to determine the frequency responses associated with each of the tones.
摘要翻译：测试系统和方法包括测试信号发生器，用于产生具有均匀分布在具有特定带宽的宽带上的多个音调的测试信号。该测试信号基于用户指定的测试信号参数（例如，使用正交频分复用（OFDM）扩频技术）生成并被处理（例如，从数字到模拟或被转换到具有相同的带宽），因此它适合于应用于被测试的特定设备，并且使得该音调考虑到被测设备的宽带操作的全频率范围。在将其应用于被测设备之后，根据需要对所得到的输出信号进行捕获，处理（例如，转换回数字或移回到初始宽带），并进行分析，以便确定与每个音调。

99. 发明授权

US09194911B2 Hardware-efficient on-chip calibration of analog/RF through sub-sampling 有权
标题翻译：通过次采样对模拟/射频进行硬件高效片上校准
公开(公告)号：US09194911B2
公开(公告)日：2015-11-24
申请号：US13341940
申请日：2011-12-31
申请人： Georgios Palaskas , Jorge Hermosillo , Marian K. Verhelst
发明人： Georgios Palaskas , Jorge Hermosillo , Marian K. Verhelst
IPC分类号： G01R31/3167 , G01R31/3181
CPC分类号： G01R31/31813
摘要： A digital on-die-test engine (OTE) generates stimuli signals for an analog/RF circuit, where the OTE is embedded within the circuitry. The stimuli signals are injected into the circuit, feed through the circuit, and are received back into the OTE for analysis. The OTE includes an input subsystem to receive signals from various locations throughout the circuit. The received signals are sub-sampled before being tested. The OTE includes memory-aware and memory-less algorithms for testing the signals. The OTE is capable of changing the configuration of the circuit, where needed, following the tests.
摘要翻译：数字在线测试引擎（OTE）为模拟/ RF电路产生刺激信号，其中OTE嵌入在电路内。刺激信号被注入到电路中，馈送通过电路，并被接收回到OTE进行分析。 OTE包括一个输入子系统，用于从整个电路的不同位置接收信号。在测试之前对接收的信号进行子采样。 OTE包括用于测试信号的内存感知和无内存算法。测试后，OTE能够根据需要改变电路的配置。

100. 发明授权

US08839062B2 Incremental modification of an error detection code background of the invention 有权
标题翻译：本发明的错误检测码背景的增量修改
公开(公告)号：US08839062B2
公开(公告)日：2014-09-16
申请号：US13348453
申请日：2012-01-11
申请人： Lior Aronovich , Michael Hirsch , Shmuel T. Klein , Yair Toaff
发明人： Lior Aronovich , Michael Hirsch , Shmuel T. Klein , Yair Toaff
IPC分类号： G01R31/316 , G06F11/25 , G01R31/3167
CPC分类号： G01R31/3167 , G06F11/1004 , H03M13/093
摘要： Exemplary method, system, and computer program product embodiments for an incremental modification of an error detection code operation are provided. In one embodiment, by way of example only, for a data block requiring a first error detection code (EDC) value to be calculated and verified and is undergoing modification for at least one randomly positioned sub-blocks that becomes available and modified in independent time intervals, a second EDC value is calculated for each of the randomly positioned sub-blocks. An incremental effect of the second EDC value is applied for calculating the first EDC value and for recalculating the first EDC value upon replacing at least one of the randomly positioned sub-blocks. The resource consumption is proportional to the size of at least one of the randomly positioned sub-blocks that are added and modified. Additional system and computer program product embodiments are disclosed and provide related advantages.
摘要翻译：提供了用于错误检测码操作的增量修改的示例性方法，系统和计算机程序产品实施例。在一个实施例中，仅作为示例，对于需要计算和验证第一错误检测码（EDC）值的数据块，并且对于在独立时间变得可用和修改的至少一个随机定位的子块正在进行修改间隔，为每个随机定位的子块计算第二EDC值。应用第二EDC值的增量效应来计算第一EDC值，并且在替换随机定位的子块中的至少一个时重新计算第一EDC值。资源消耗与添加和修改的随机定位的子块中的至少一个的大小成比例。公开了附加的系统和计算机程序产品实施例并提供相关的优点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式