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91. 发明申请

US20040130942A1 Data retention for a localized trapping non-volatile memory 审中-公开
标题翻译：本地捕获非易失性存储器的数据保留
公开(公告)号：US20040130942A1
公开(公告)日：2004-07-08
申请号：US10336505
申请日：2003-01-02
申请人： Macronix International Co., Ltd.
发明人： Chih Chieh Yeh , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C016/04
CPC分类号： G11C16/3404 , G11C16/3454 , H01L29/7923
摘要： The invention advantageously provides a device and method for optimal data retention in a trapping nonvolatile memory cell. A preferred embodiment of the invention provides a trapping nonvolatile memory cell comprising a semiconductor substrate further comprising a source, a drain spaced from the source, and a channel region formed between the source and the drain, a first isolating layer overlying the channel region, a nonconducting charge trapping layer overlying the first isolating layer and trapping electrical charges therein using charge injection, a second isolating layer overlying the trapping layer, and a gate overlying the second isolating layer. After the charges are trapped in the trapping layer, some of the trapped charges are detrapped using electrical field enhanced electron detrapping technique. The charges in the trapping layer are repeatedly trapped and detrapped shallow traps until a desired number of the deep traps are stored in the trapping layer.
摘要翻译：本发明有利地提供了一种用于在捕获非易失性存储器单元中优化数据保持的装置和方法。本发明的优选实施例提供了一种捕获非易失性存储单元，其包括半导体衬底，其还包括源极，与源极间隔开的漏极以及形成在源极和漏极之间的沟道区域，覆盖沟道区域的第一隔离层，覆盖在第一绝缘层上并且使用电荷注入捕获电荷的非导电电荷捕获层，覆盖在捕获层上的第二隔离层和覆盖在第二隔离层上的栅极。在电荷被捕获在捕获层中之后，使用电场增强的电子去除技术去除捕获的一些电荷。捕集层中的电荷被重复捕获并除去浅陷阱，直到所需数量的深陷阱存储在捕获层中。

92. 发明申请

US20040120188A1 NOVEL TWO-TRANSISTOR FLASH CELL FOR LARGE ENDURANCE APPLICATION 有权
标题翻译：用于大容量应用的新型双向晶体管闪存单元
公开(公告)号：US20040120188A1
公开(公告)日：2004-06-24
申请号：US10323982
申请日：2002-12-19
申请人： Taiwan Semiconductor Manufacturing Company
发明人： Yu-Der Chih
IPC分类号： G11C016/04
CPC分类号： G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/66825 , H01L29/792
摘要： An nonvolatile memory device having improved endurance is comprised of an array of nonvolatile memory cells arranged in rows and columns. Each memory cell of each row is connected to a word line and a source select line, and each memory cell of each column connected to a first bit line and a second bit line. Each memory cell is composed of a first transistor and second transistor. The first and second transistors have control gate connected to the word line receive a word line voltage, a source connected the source select line to receive a source line voltage, and a floating gate onto which an electronic charge is placed representing a data bit stored within the nonvolatile memory device. The first transistor has a drain connected the first bit line to receive a first bit line voltage and the second transistor a drain connected to the second bit line to receive a second bit line voltage. Each memory cell has a floating gate connector joining the floating gate of the second transistor to the floating gate of the second transistor. The nonvolatile memory device has a voltage controller programs the each memory cell by programming the first transistor and reading the second transistor. Alternately the voltage controller employs a two step programming method by programming the first transistor for a short period of time and then programming the second transistor for second short period of time and then reading from the second transistor.
摘要翻译：具有改进的耐久性的非易失性存储器件包括以行和列布置的非易失性存储单元的阵列。每行的每个存储单元连接到字线和源选择线，并且每列的每个存储单元连接到第一位线和第二位线。每个存储单元由第一晶体管和第二晶体管构成。第一和第二晶体管具有连接到字线的控制栅极接收字线电压，源极连接源极线以接收源极线电压，以及浮置栅极，其上放置电子电荷表示存储在其中的数据位非易失性存储器件。第一晶体管具有连接第一位线的漏极以接收第一位线电压，而第二晶体管漏极连接到第二位线以接收第二位线电压。每个存储单元具有将第二晶体管的浮置栅极连接到第二晶体管的浮置栅极的浮动栅极连接器。非易失性存储器件具有电压控制器，通过编程第一晶体管并读取第二晶体管来对每个存储单元进行编程。或者，电压控制器采用两步编程方法，通过在短时间段内对第一晶体管进行编程，然后对第二晶体管编程第二短时间段，然后从第二晶体管读取。

93. 发明申请

US20040100849A1 METHOD OF UTILIZING A PLURALITY OF VOLTAGE PULSES TO PROGRAM NON-VOLATILE MEMORY ELEMENTS AND RELATED EMBEDDED MEMORIES 有权
标题翻译：利用多重电压脉冲编程非易失性存储器元件和相关嵌入式存储器的方法
公开(公告)号：US20040100849A1
公开(公告)日：2004-05-27
申请号：US10305735
申请日：2002-11-27
发明人： David Novosel , Gary S. Craig
IPC分类号： G11C011/24 , G11C007/00 , G11C016/04
CPC分类号： G11C17/16 , G11C17/18 , G11C2207/104
摘要： A method and related embedded memories are disclosed for utilizing a plurality of voltage pulses to program non-volatile memory elements. Non-volatile memory cells and associated programming methods are also disclosed that allow for the integration of non-volatile memory with other integrated circuitry utilizing the standard CMOS processing used to manufacture the CMOS circuitry. The non-volatile memory cell includes an antifuse element having a programming node and a capacitor coupled to the programming node. To write the antifuse element, a plurality of voltage pulses are used to provide a rapid series of charge flows through the antifuse element. The antifuse element includes a MOS transistor having its source and drain connected to one or more voltage levels, having a gate that provides the programming node, and having a dielectric layer that provides an antifuse function by breaking down when subjected to a plurality of voltage pulses applied through the capacitor element.
摘要翻译：公开了一种利用多个电压脉冲来编程非易失性存储器元件的方法和相关的嵌入式存储器。还公开了非易失性存储器单元和相关联的编程方法，其允许使用用于制造CMOS电路的标准CMOS处理将非易失性存储器与其它集成电路集成。非易失性存储单元包括具有编程节点和耦合到编程节点的电容器的反熔丝元件。为了写入反熔丝元件，使用多个电压脉冲来提供通过反熔丝元件的快速一系列电荷流。反熔丝元件包括其源极和漏极连接到一个或多个电压电平的MOS晶体管，其具有提供编程节点的栅极，并且具有电介质层，当经受多个电压脉冲时通过分解来提供反熔丝功能通过电容器元件施加。

94. 发明申请

US20040100823A1 Mode selection in a flash memory device 有权
公开(公告)号：US20040100823A1
公开(公告)日：2004-05-27
申请号：US10301409
申请日：2002-11-21
申请人： Micron Technology, Inc.
发明人： Frankie F. Roohparvar
IPC分类号： G11C016/04 , G11C007/00 , G11C011/34
CPC分类号： G11C7/1021 , G11C7/1045 , G11C16/26
摘要： A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selecting the page mode causes the device to output selected memory pages.

95. 发明申请

US20040080980A1 Methods of programming non-volatile semiconductor memory devices including coupling voltages and related devices 有权
标题翻译：编程非易失性半导体存储器件包括耦合电压和相关器件的方法
公开(公告)号：US20040080980A1
公开(公告)日：2004-04-29
申请号：US10640082
申请日：2003-08-13
发明人： Chang-Hyun Lee
IPC分类号： G11C016/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/12 , G11C16/3418
摘要： A non-volatile memory device may include a string of serially connected memory cell transistors with each memory cell transistor of the string being connected to a different word line. The non-volatile memory device may be programmed by applying a pass voltage to a first word line connected to a first memory cell transistor of the string, by applying a coupling voltage to a second word line connected to a second memory cell transistor of the string, and by applying a program voltage to a third word line connected to a third memory cell transistor of the string. More particularly, the coupling voltage can be greater than a ground voltage of the memory device, and the pass voltage and the coupling voltage can be different. In addition, the program voltage can be applied to the third word line while applying the pass voltage to the first word line and while applying the coupling voltage to the second word line, and the third memory cell transistor can be programmed responsive to applying the program voltage to the third word line wherein the second memory cell transistor is between the first and third memory cell transistors of the serially connected string. Related devices are also discussed.
摘要翻译：非易失性存储器件可以包括一串串联的存储单元晶体管，其中串的每个存储单元晶体管连接到不同的字线。可以通过向连接到串的第一存储单元晶体管的第一字线施加通过电压来对非易失性存储器件进行编程，通过向连接到串的第二存储单元晶体管的第二字线施加耦合电压并且通过对连接到串的第三存储单元晶体管的第三字线施加编程电压。更具体地，耦合电压可以大于存储器件的接地电压，并且通过电压和耦合电压可以不同。此外，可以将编程电压施加到第三字线，同时将通过电压施加到第一字线，同时将耦合电压施加到第二字线，并且第三存储单元晶体管可以响应于应用程序而被编程电压到第三字线，其中第二存储单元晶体管位于串行连接的串的第一和第三存储单元晶体管之间。还讨论了相关设备。

96. 发明申请

US20040080979A1 Nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor 有权
标题翻译：具有三电平存储器单元的非易失性半导体存储器及其编程和读取映射电路
公开(公告)号：US20040080979A1
公开(公告)日：2004-04-29
申请号：US10280939
申请日：2002-10-25
申请人： Nexflash Technologies, Inc.
发明人： Eungjoon Park
IPC分类号： G11C016/04
CPC分类号： G11C16/26 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C2211/5641
摘要： A memory uses multiple threshold levels in a memory cell that are not a power of two, and further uses a cell mapping technique wherein the read mapping is only a partial function The domain of read states for a single three-level memory cell, for example, has three states, but only two of them can be uniquely mapped to a bit. The domain of read states for two three-level memory cell, for example, has nine states, but only eight of them can be uniquely mapped to three bits. Although the read mapping is only partial, the voltage margin for the three-level memory cells is larger that the voltage margin available in the commonly used four-level memory cells. This increased voltage margin facilitates memory cell threshold voltage sensing, thereby increasing the reliability of the memory. Memory reliability may be further improved by increasing the voltage margin between the memory cell 0 state and the 1 state relative to the voltage margin between the 1 state and the 2 state, which more effectively accommodates charge loss from the 0 state through electron leakage. Asymmetrical read and program mapping may also be used to improve read reliability in the presence of ground noise or VCC noise.
摘要翻译：存储器在不是2的幂的存储器单元中使用多个阈值电平，并且还使用单元映射技术，其中读取映射仅是部分功能。例如，单个三电平存储器单元的读取状态域，有三个状态，但只有两个可以被唯一地映射到一点。例如，两个三电平存储单元的读状态域有九个状态，但只有八个可以唯一地映射到三位。虽然读取映射仅仅是部分的，但三电平存储单元的电压裕度大于常用四电平存储单元中可用的电压余量。这种增加的电压裕度便于存储单元阈值电压感测，从而增加存储器的可靠性。通过相对于1状态和2状态之间的电压裕度增加存储单元0状态和1状态之间的电压裕度可以进一步提高存储器可靠性，这更有效地适应从0状态通过电子泄漏的电荷损失。不对称读取和程序映射也可用于在存在接地噪声或VCC噪声的情况下提高读取可靠性。

97. 发明申请

US20040066670A1 ONE-TIME-PROGRAMMABLE BIT CELL WITH LATCH CIRCUIT HAVING SELECTIVELY PROGRAMMABLE FLOATING GATE TRANSISTORS 有权
标题翻译：具有选择性可编程浮动栅极晶体管的单片电路的一次可编程位元件
公开(公告)号：US20040066670A1
公开(公告)日：2004-04-08
申请号：US10264756
申请日：2002-10-04
发明人： Daran DeShazo , Agustinus Sutandi , Jason Stevens
IPC分类号： G11C016/04
CPC分类号： G11C16/0441 , G11C17/14
摘要： An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.
摘要翻译： OTP位单元包括交叉耦合的反相器的锁存电路。在每个逆变器中插入浮置栅极PMOS晶体管。一个或另一个浮置栅极PMOS晶体管通过包含的编程电路进行编程，使得锁存电路的差分输出提供相应的每次读取时相同的逻辑状态。为了对所选择的浮置栅极PMOS晶体管进行编程，适当的写入输入被施加到编程电路，同时向OTP位单元的高参考电压升高到使所选择的浮置栅极PMOS晶体管被编程的电平。

98. 发明申请

US20040057288A1 Control method of non-volatile semiconductor memory cell and non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器单元和非易失性半导体存储器件的控制方法
公开(公告)号：US20040057288A1
公开(公告)日：2004-03-25
申请号：US10665205
申请日：2003-09-22
申请人： FUJITSU LIMITED
发明人： Shozo Kawabata
IPC分类号： G11C016/04
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/3459
摘要： It is intended to provide control method and a nonvolatile semiconductor memory device capable of erase operation or write operation in high speed securing reliability without applying excessive electric field. An operation unit consists of a plurality of operation cycles each of which has a bias-application period and a verification period. Addition voltage nullV is added to each operation unit as bias voltage, whereby a write operation can be carried out with characteristic of injected current IFG that is uniform among respective operation units duration of which are generally same. In this case, duration of operation cycles are shortened by each operation unit and duration of verification periods are shortened so as to avoid a situation such that a write operation completes in the middle of a bias-application period and after that, another write operation continues to cause excessive voltage stress on non-volatile semiconductor memory cells.
摘要翻译：旨在提供控制方法和非易失性半导体存储器件，其能够在不施加过大电场的情况下以高速确保可靠性进行擦除操作或写入操作。操作单元由多个操作循环组成，每个操作循环具有偏置施加周期和验证周期。将加法电压DeltaV作为偏置电压加到每个操作单元上，由此可以以相同操作单元的持续时间大致相同的注入电流IFG的特性进行写入操作。在这种情况下，通过每个操作单元缩短操作周期的持续时间，并且缩短验证周期的持续时间，以避免在偏置施加期间的中间写入操作完成的情况，之后另一个写入操作继续以对非易失性半导体存储单元造成过大的电压应力。

99. 发明申请

US20040052113A1 Method and apparatus for preventing overtunneling in pFET-based nonvolatile memory cells 有权
标题翻译：用于防止基于pFET的非易失性存储单元中的过度隧穿的方法和装置
公开(公告)号：US20040052113A1
公开(公告)日：2004-03-18
申请号：US10245183
申请日：2002-09-16
申请人： Impinj, Inc., a Delaware Corporation
发明人： Christopher J. Diorio , Chad Lindhorst , Shail Srinivas , Alberto Pesavento , Troy Gilliland
IPC分类号： G11C016/04 , G11C011/34
CPC分类号： G11C16/3477 , G11C16/3404 , G11C16/3468 , G11C16/3472
摘要： Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.
摘要翻译：方法和装置可以防止基于pFET的非易失性浮动栅极存储器（NVM）单元中的超导。在其中从基于pFET的NVM单元的浮置栅极去除电荷载流子的隧穿过程中，监测存储单元晶体管的沟道电流，并将其与在注入中维持导通通道所需的预定最小沟道电流进行比较晶体管的存储单元。当监测的通道电流下降到预定的最小通道电流以下时，电荷载流子通过冲击电离热电子注入（IHEI）注入到浮动栅极上，从而避免了超导。

100. 发明申请

US20040047186A1 Erasing method for non-volatile memory 有权
公开(公告)号：US20040047186A1
公开(公告)日：2004-03-11
申请号：US10289866
申请日：2002-11-06
发明人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu , Samuel C. Pan
IPC分类号： G11C016/04
CPC分类号： G11C16/14
摘要： An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.

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