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91. 发明授权

US5811736A Electronic circuit cards with solder-filled blind vias 失效
标题翻译：带焊料填充盲孔的电子电路卡
公开(公告)号：US5811736A
公开(公告)日：1998-09-22
申请号：US699362
申请日：1996-08-19
申请人： John Matthew Lauffer , Richard Charles Senger
发明人： John Matthew Lauffer , Richard Charles Senger
IPC分类号： H05K1/00 , H05K1/11 , H05K3/00 , H05K3/22 , H05K3/34 , H05K3/40 , H05K3/46 , H01R9/09
CPC分类号： H05K3/3442 , H05K1/112 , H05K3/0023 , H05K3/225 , H05K3/4652 , H05K1/0292 , H05K2201/0305 , H05K2201/0355 , H05K2201/09472 , H05K2201/10636 , H05K2203/0551 , H05K3/3452 , H05K3/4038 , Y02P70/611 , Y02P70/613
摘要： A printed circuit board has a plurality of layers. A first surface land is formed on an inner layer. A dielectric material is laminated on the inner layer. A second surface land is formed on the dielectric material overlapping the inner surface land or positioned along the border of the inner surface land. A hole is etched in the dielectric material exposing the first surface land to the second surface land. The second surface land does not completely surround the hole. A component lead is positioned over the second surface land. Solder is reflowed into the hole to interconnect the surface lands to each other and to the component lead. Because the second surface land does not completely surround the hole, the solder does not bridge across the hole and thereby forms a solid connection between the first and second surface lands.
摘要翻译：印刷电路板具有多个层。第一表面焊盘形成在内层上。介电材料层叠在内层上。第二表面焊盘形成在与内表面焊盘重叠的介电材料上，或者沿着内表面焊盘的边界定位。在电介质材料中蚀刻孔，将第一表面焊盘暴露于第二表面焊盘。第二个表面土地没有完全围绕着洞。部件引线定位在第二表面焊盘上。焊料回流到孔中以将表面焊盘互相连接并连接到部件引线。由于第二表面焊盘不完全围绕孔，所以焊料不穿过孔，从而在第一和第二表面焊盘之间形成牢固的连接。

92. 发明授权

US5746868A Method of manufacturing multilayer circuit substrate 失效
公开(公告)号：US5746868A
公开(公告)日：1998-05-05
申请号：US503917
申请日：1995-07-19
申请人： Tomoyuki Abe
发明人： Tomoyuki Abe
IPC分类号： H05K1/09 , B22F7/08 , H01L21/48 , H05K3/02 , H05K3/10 , H05K3/24 , H05K3/28 , H05K3/34 , H05K3/38 , H05K3/40 , H05K3/46 , B32B31/18 , B05D5/12 , B32B31/26
CPC分类号： H05K3/4617 , B22F7/08 , H01L21/4857 , H01L21/486 , H05K3/102 , H05K3/247 , H05K3/4069 , H05K3/4664 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H05K1/095 , H05K2201/0305 , H05K2201/0355 , H05K2201/0394 , H05K2203/0191 , H05K2203/1131 , H05K2203/1327 , H05K3/28 , H05K3/3473 , H05K3/388 , H05K3/4038 , Y10T156/1057 , Y10T29/49155
摘要： A method of manufacturing a multilayer circuit substrate includes a process of forming via holes in an insulating film, a process of applying an electrically conducting paste obtained by having ultra-fine metal particles disperse in a solvent onto an insulating film, and a process of forming vias composed of a sintered product of ultra-fine metal particles in the via holes by removing the solvent and also sintering the ultra-fine metal particles. The sintered products of the ultra-fine metal particles on the insulating layer is removed (or patterned) by peeling off the protective film stuck to the insulating layer.

93. 发明授权

US5640761A Method of making multi-layer circuit 失效
标题翻译：制作多层电路的方法
公开(公告)号：US5640761A
公开(公告)日：1997-06-24
申请号：US478420
申请日：1995-06-07
申请人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
发明人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
IPC分类号： H01L21/48 , H01L23/538 , H05K1/00 , H05K3/40 , H05K3/42 , H05K3/46 , H05K3/36
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H01L23/5385 , H01R12/523 , H05K1/0287 , H05K1/029 , H01L2924/0002 , H01L2924/09701 , H05K1/0298 , H05K2201/0195 , H05K2201/0305 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09609 , H05K2201/09945 , H05K2201/10378 , H05K2201/10666 , H05K2203/175 , H05K3/4038 , H05K3/4069 , H05K3/4602 , H05K3/4623 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottom end of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.
摘要翻译：多层电路组件通过在其顶表面上具有接触的电路板堆叠，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而制成。端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。这形成延伸穿过多个面板的复合垂直导体。面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。还提供了具有贯通导体的电路板前体及其制造方法。

94. 发明授权

US5630271A Method of forming a wiring pattern for an electronic circuit on a general-purpose circuit board 失效
标题翻译：在通用电路板上形成用于电子电路的布线图案的方法
公开(公告)号：US5630271A
公开(公告)日：1997-05-20
申请号：US534994
申请日：1995-09-27
申请人： Kei Suzuki
发明人： Kei Suzuki
IPC分类号： H05K1/11 , H05K1/00 , H05K1/02 , H05K3/22 , H05K3/34 , H05K3/02
CPC分类号： H05K1/0293 , H05K1/0287 , H05K1/116 , H05K2201/0305 , H05K2201/09609 , H05K2201/09645 , H05K2201/09663 , H05K2203/0195 , H05K2203/1115 , H05K2203/175 , H05K3/3447 , Y10T29/49155 , Y10T29/49162
摘要： A unique general-purpose circuit board and a unique burning jig implement a wiring pattern for the trial manufacture of a new electronic circuit. The circuit board is implemented as an insulative plate on which horizontal and vertical parallel conductive lines are provided, and in which through holes are formed at the junctions of the lines. Each through hole is surrounded by four conductive portions insulated from each other and each being connected to a particular conductive line. The burning jig has a flat base and burning pins studded on the base and each corresponding to one of the through holes. Each burning pin has four metal pieces at one end thereof. The four metal pieces are insulated from each other and respectively correspond to the four conductive portions surrounding a single through hole. After the pins of the jig have been inserted into the through holes of the circuit board, the line connecting any nearby through holes is burned off by a current fed to between the metal pieces of the corresponding pins.
摘要翻译：独特的通用电路板和独特的燃烧夹具实现了用于试制新电子电路的布线图案。电路板实现为绝缘板，其上设有水平和垂直平行导线，并且其中在线的接合处形成有通孔。每个通孔被彼此绝缘的四个导电部分围绕，并且每个通孔连接到特定的导电线。燃烧夹具具有平坦的基部，并且在基部上分布有燃烧的销，并且每个对应于一个通孔。每个燃烧销在其一端具有四个金属片。四个金属片彼此绝缘，并且分别对应于围绕单个通孔的四个导电部分。在夹具的销插入电路板的通孔中之后，连接任何附近的通孔的线被馈送到相应销的金属片之间的电流而被烧掉。

95. 发明授权

US5583321A Multi-layer circuit construction methods and structures with customization features and components for use therein 失效
标题翻译：多层电路构造方法和结构，具有用于其中的定制特征和组件
公开(公告)号：US5583321A
公开(公告)日：1996-12-10
申请号：US443706
申请日：1995-05-15
申请人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
发明人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
IPC分类号： H01L21/48 , H01L23/538 , H05K1/00 , H05K3/40 , H05K3/42 , H05K3/46 , H05K1/02
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H01L23/5385 , H01R12/523 , H05K1/0287 , H05K1/029 , H01L2924/0002 , H01L2924/09701 , H05K1/0298 , H05K2201/0195 , H05K2201/0305 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09609 , H05K2201/09945 , H05K2201/10378 , H05K2201/10666 , H05K2203/175 , H05K3/4038 , H05K3/4069 , H05K3/4602 , H05K3/4623 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.
摘要翻译：多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。这形成延伸穿过多个面板的复合垂直导体。面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。还提供了具有贯通导体的电路板前体及其制造方法。

96. 发明授权

US5570504A Multi-Layer circuit construction method and structure 失效
标题翻译：多层电路构造方法与结构
公开(公告)号：US5570504A
公开(公告)日：1996-11-05
申请号：US393165
申请日：1995-02-21
申请人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
发明人： Thomas H. DiStefano , Igor Y. Khandros , Gary W. Grube
IPC分类号： H01L21/48 , H01L23/538 , H05K1/00 , H05K3/40 , H05K3/42 , H05K3/46 , H05K3/36
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H01L23/5385 , H01R12/523 , H05K1/0287 , H05K1/029 , H01L2924/0002 , H01L2924/09701 , H05K1/0298 , H05K2201/0195 , H05K2201/0305 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09609 , H05K2201/09945 , H05K2201/10378 , H05K2201/10666 , H05K2203/175 , H05K3/4038 , H05K3/4069 , H05K3/4602 , H05K3/4623 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.
摘要翻译：多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。这形成延伸穿过多个面板的复合垂直导体。面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。还提供了具有贯通导体的电路板前体及其制造方法。

97. 发明授权

US5558928A Multi-layer circuit structures, methods of making same and components for use therein 失效
标题翻译：多层电路结构，制造方法及其中使用的组件
公开(公告)号：US5558928A
公开(公告)日：1996-09-24
申请号：US278426
申请日：1994-07-21
申请人： Thomas H. DiStefano , Scott G. Ehrenberg , Igor Y. Khandros
发明人： Thomas H. DiStefano , Scott G. Ehrenberg , Igor Y. Khandros
IPC分类号： H01L21/48 , H01L23/538 , H05K1/00 , H05K1/02 , H05K3/40 , H05K3/42 , H05K3/46 , B32B9/00
CPC分类号： H05K3/462 , H01L21/4857 , H01L23/5383 , H01R12/523 , H05K1/0287 , H05K1/029 , H01L2924/0002 , H01L2924/09701 , H05K1/0298 , H05K2201/0305 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2201/09609 , H05K2201/09945 , H05K2201/10378 , H05K2203/175 , H05K3/4038 , H05K3/4069 , H05K3/4602 , H05K3/4623 , Y10T29/49126 , Y10T29/49156 , Y10T29/49165 , Y10T428/239 , Y10T428/24917
摘要： A multi-layer circuit panel assembly is formed by laminating circuit panels with interposers incorporating flowable conductive material at interconnect locations and a flowable dielectric materials at locations other than the interconnect locations. Excess materials are captured in reservoirs such as within vias in the circuit panels and apertures in interior elements within the interposers. The flowable materials of the interposers, together with the reservoirs, allow the interposers to compress and take up tolerances in the components. The flowable dielectric material encapsulates conductors on the surfaces of the circuit panels.
摘要翻译：多层电路板组件通过层叠具有在互连位置处并入可流动导电材料的插入件的电路板和在互连位置之外的位置处的可流动电介质材料形成。过多的材料被捕获在储存器中，例如电路板中的通孔内和插入件内的内部元件中的孔。插入件的可流动材料与储存器一起允许内插件压缩并占据部件中的公差。可流动的电介质材料封装电路板表面上的导体。

98. 发明授权

US5468345A Method of making a high-definition printed circuit 失效
标题翻译：制作高分辨印刷电路的方法
公开(公告)号：US5468345A
公开(公告)日：1995-11-21
申请号：US237835
申请日：1994-05-04
申请人： Ronald K. Kirby , James W. Watson
发明人： Ronald K. Kirby , James W. Watson
IPC分类号： H05K1/00 , H05K3/00 , H05K3/06 , H05K3/10 , H05K3/38 , B44C1/22 , C23F1/02
CPC分类号： H05K3/108 , H05K3/062 , H05K1/0393 , H05K2201/0305 , H05K2201/0317 , H05K2203/0361 , H05K2203/043 , H05K2203/1545 , H05K3/0052 , H05K3/388
摘要： A method of making printed circuit boards in a continuous process. The method uses copper base metal sputtered onto a substrate. This base metal is much thinner than the base metal normally used in printed circuit processes and ultimately allows a greater number of conductors per unit of length to be made on the boards.
摘要翻译：在连续工艺中制造印刷电路板的方法。该方法使用溅射到基底上的铜基金属。这种母材比通常在印刷电路工艺中使用的母材要薄得多，并且最终允许在板上制造每单位长度的更多数量的导体。

99. 发明授权

US5445311A Electrical interconnection substrate with both wire bond and solder contacts, and fabrication method 失效
标题翻译：具有引线接合和焊接触点的电气互连基板，以及制造方法
公开(公告)号：US5445311A
公开(公告)日：1995-08-29
申请号：US324271
申请日：1994-10-13
申请人： Philip A. Trask , Vincent A. Pillai , Thomas J. Gierhart
发明人： Philip A. Trask , Vincent A. Pillai , Thomas J. Gierhart
IPC分类号： B23K1/00 , B23K1/018 , B23K1/08 , H01L21/48 , H01L21/60 , H01L23/538 , H01L25/065 , H05K3/00 , H05K3/06 , H05K3/24 , H05K3/28 , H05K3/32 , H05K3/34 , B23K31/00 , H01L21/02
CPC分类号： H01L24/48 , B23K1/0016 , B23K1/018 , B23K1/08 , B23K1/085 , H01L21/4846 , H01L21/4864 , H01L23/538 , H01L24/03 , H01L24/05 , H01L24/80 , H01L24/81 , H01L25/0655 , H05K3/243 , H05K3/3452 , H05K3/3468 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05556 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/16 , H01L2224/45144 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/81801 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H05K2201/0154 , H05K2201/0305 , H05K2201/0391 , H05K2203/0361 , H05K2203/044 , H05K2203/049 , H05K2203/0585 , H05K3/0041 , H05K3/067 , H05K3/28 , H05K3/328 , Y10T29/49144
摘要： An electrical interconnection substrate (20) is prepared to receive both wire bonded and soldered connections (60,64,66) by forming a dielectric solder mask (30) over the substrate (20), with openings (36) in the mask (30) to expose the contact pads (22) for which soldered connections are desired. The substrate (20) is exposed to a molten solder alloy (44) in a wave soldering process that dissolves the wire bonding material (28) (preferably gold) from the exposed pads (22) and deposits solder bonding pads (52) in its place. Excess solder is then removed from the substrate, and openings (54) are formed through the solder mask (30) to expose the wire bond contact pads (22'). The selective dissolving of gold bonding layers (28) and their replacement by solder pads (52) prevents the establishment of brittle gold-solder intermetallics, and the deposited solder (52) requires no further heat treatment for correct alloy formation.
摘要翻译：制备电互连衬底（20）以通过在衬底（20）上形成电介质焊接掩模（30）以在掩模（30）中形成开口（36）来接收引线接合和焊接连接（60,66,66））以暴露需要焊接连接的接触焊盘（22）。在波导焊接工艺中，将衬底（20）暴露于熔融焊料合金（44）中，该焊接工艺使焊接接合材料（28）（优选为金）从暴露的焊盘（22）溶解并将焊接焊盘（52）沉积在其中地点。然后从衬底去除过量的焊料，并且通过焊料掩模（30）形成开口（54），以暴露引线接合焊盘（22'）。金键合层（28）的选择性溶解及其被焊盘（52）的替代防止了脆性金 - 焊料金属间化合物的建立，并且沉积的焊料（52）不需要进一步的热处理来正确的合金形成。

100. 发明授权

US5433819A Method of making circuit boards 失效
标题翻译：电路板制作方法
公开(公告)号：US5433819A
公开(公告)日：1995-07-18
申请号：US67732
申请日：1993-05-26
申请人： Mark T. McMeen
发明人： Mark T. McMeen
IPC分类号： H05K1/00 , H05K1/11 , H05K3/06 , H05K3/28 , H05K3/38 , H05K3/40 , B44C1/22 , C23F1/02
CPC分类号： H05K1/112 , H05K3/281 , H05K3/384 , H05K3/4084 , H05K1/0393 , H05K1/118 , H05K2201/0305 , H05K2201/0338 , H05K2201/0355 , H05K2201/0394 , H05K2201/0397 , H05K2201/09472 , H05K2203/0361 , H05K2203/063 , H05K2203/0723 , H05K2203/1545 , H05K2203/1572 , H05K3/061 , H05K3/284 , H05K3/386 , H05K3/4038 , H05K3/4069
摘要： A method of making circuit boards is disclosed that is suitable for use in a high-volume automated processing plant. The method can be used to produce either single-sided or double-sided circuit boards with access windows allowing electrical access and connection between traces from both sides. In the process, access holes are punched in a coverfilm. A copper sheet having a tin plating on one side is laminated to the coverfilm, with the tin side facing the coverfilm. A pattern representing a circuit is screened on the resulting laminate with a UV-curable resist, developed in a UV dryer, and then the unprotected copper is etched away. The remaining tin is then removed with solder stripping agent, and the resulting circuit is protected with a coverfilm. The process can be applied to large rolls of materials in an automated process, with large numbers of circuits applied to the laminated board. The circuits can then be punched out of the web with a hydraulic press in large numbers. The use of two copper sheets and double-sided covering (i.e., having adhesive on both sides) in a slightly modified process permits the efficient manufacture of double-sided circuit boards.
摘要翻译：公开了一种适用于大容量自动化处理设备的制造电路板的方法。该方法可用于生产具有访问窗口的单面或双面电路板，允许电连接和两侧迹线之间的连接。在此过程中，穿孔孔被覆盖在覆盖膜中。将一面具有镀锡的铜片层压到覆盖膜上，锡面朝向覆盖膜。用UV干燥器显影的UV可固化抗蚀剂在所得层压板上筛选代表电路的图案，然后将未保护的铜蚀刻掉。然后用焊料剥离剂除去剩余的锡，所得到的电路用覆盖膜保护。该过程可以在自动化过程中应用于大量材料，其中大量电路施加到层压板上。然后，可以用液压机将电路从网中冲出大量。在稍微改进的过程中使用两个铜片和双面覆盖物（即在两侧具有粘合剂）允许双面电路板的有效制造。

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