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91. 发明授权

US08243869B2 Burst mode clock and data recovery circuit and method 失效
标题翻译：突发模式时钟和数据恢复电路及方法
公开(公告)号：US08243869B2
公开(公告)日：2012-08-14
申请号：US11604748
申请日：2006-11-28
申请人： Amiad Dvir , Raviv Weber , David Avishai , Alex Goldstein , Igor Elkanovich , Gal Sitton , Michael Balter
发明人： Amiad Dvir , Raviv Weber , David Avishai , Alex Goldstein , Igor Elkanovich , Gal Sitton , Michael Balter
IPC分类号： H03D3/24
CPC分类号： H04L7/0337 , H04L7/0025 , H04L7/005
摘要： Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.
摘要翻译：突发模式时钟和数据恢复（BCDR）电路和方法，能够快速地对无源光网络（PON）业务进行数据恢复。从输入突发数据信号产生过采样数据流，相位内插器使用参考时钟和相位信息产生采样时钟信号。相位估计单元（PEU）确定过采样数据流中的相位误差; 并且相位检索单元在接收输入的突发数据信号之前，将相位内插器与输入的脉冲串数据信号的各自的相位信息相对应。

92. 发明申请

US20120200322A1 CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE 有权
标题翻译：时钟插入延迟独立接口
公开(公告)号：US20120200322A1
公开(公告)日：2012-08-09
申请号：US13022824
申请日：2011-02-08
申请人： Stefan Block , Herbert Preuthen , Juergen Dirks
发明人： Stefan Block , Herbert Preuthen , Juergen Dirks
IPC分类号： H03L7/00
CPC分类号： H04L7/0337 , G06F1/06 , G06F1/08
摘要： Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.
摘要翻译：这里公开了具有多时钟接口的多时钟接口，集成电路及其模块，以及具有与上述电路对应的单元的库。在一个实施例中，多时钟接口包括：（1）多时钟复位同步器，被配置为接收第一外部时钟信号和作为第一时钟信号的倍数的第二外部时钟信号，复位同步器被配置为使复位第一外部时钟信号和第二外部时钟信号，并且基于其产生复位释放信号;以及（2）被配置为接收复位释放信号和第二时钟信号的多相时钟发生器，所述多相时钟发生器被配置为产生基于复位释放信号的第二时钟信号的多个时钟相位。

93. 发明申请

US20120182026A1 CLOCK GENERATING APPARATUS, TEST APPARATUS AND CLOCK GENERATING METHOD 有权
标题翻译：时钟发生装置，测试装置和时钟发生方法
公开(公告)号：US20120182026A1
公开(公告)日：2012-07-19
申请号：US13181526
申请日：2011-07-13
申请人： Nobuei WASHIZU
发明人： Nobuei WASHIZU
IPC分类号： G01R23/20 , H03L7/00
CPC分类号： H04L7/0337 , H03L7/0807
摘要： There is provided a clock generating apparatus for generating a recovered clock by recovering a clock from an edge of a received signal, including a recovered clock generating section that generates the recovered clock, a multi-strobe generating section that generates a plurality of strobes with different phases, in accordance with a pulse of the recovered clock, a detecting section that detects a position of an edge of the received signal relative to the strobes, by referring to values of the received signal obtained at respective timings of the strobes, and an adjusting section that adjusts a phase of the recovered clock, in accordance with the position of the edge of the received signal.
摘要翻译：提供了一种时钟产生装置，用于通过从接收信号的边缘恢复时钟来产生恢复的时钟，包括产生恢复的时钟的恢复时钟产生部分，产生具有不同的多个频闪的多选通产生部分根据恢复的时钟的脉冲，检测部分，通过参考在频闪的相应定时获得的接收信号的值，检测接收信号相对于选通脉冲的边缘的位置，以及调整根据接收信号的边缘的位置来调整恢复的时钟的相位。

94. 发明授权

US08223828B2 Methods and systems for adaptive receiver equalization 有权
标题翻译：自适应接收机均衡的方法和系统
公开(公告)号：US08223828B2
公开(公告)日：2012-07-17
申请号：US11976185
申请日：2007-10-22
申请人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
发明人： Aaron Buchwald , Xicheng Jiang , Hui Wang , Howard A. Baumer , Avanindra Madisetti
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0274 , H04L7/0337 , H04L25/03006 , H04L2025/03477 , H04L2025/03617
摘要： Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discrete-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.
摘要翻译：用于最小化模拟数据信号中的失真的方法和系统包括在接收端均衡模拟数据信号。在一个实施例中，本发明使均衡参数适应于与模拟数据信号相关联的信号路径。自适应控制逻辑由模拟和/或数字组件实现。在一个实施例中，本发明使模拟数据信号的离散时间模拟表示相等。在一个实施例中，本发明数字地控制均衡参数。在一个实施例中，所得到的均衡的模拟数据信号被数字化。在示例实现中，对模拟数据信号进行采样，测量样本的质量，并且根据需要使用数字控制来调整一个或多个均衡参数以最小化样本的失真。然后将均衡的样品数字化。本发明适用于低速模拟数据信号和多吉比特数据速率模拟信号。

95. 发明申请

US20120155585A1 SYSTEM AND METHOD FOR MULTIPLEXING A TIME-REFERENCE SIGNAL AND A FREQUENCY-REFERENCE SIGNAL 有权
标题翻译：用于多路复用时间参考信号和频率参考信号的系统和方法
公开(公告)号：US20120155585A1
公开(公告)日：2012-06-21
申请号：US12971490
申请日：2010-12-17
申请人： Joseph G. Trotta , Noah Gottfried , Richard Gammenthaler
发明人： Joseph G. Trotta , Noah Gottfried , Richard Gammenthaler
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H04J3/0614 , H04J3/0685 , H04L7/02 , H04L7/033 , H04L7/0331 , H04L7/0337
摘要： A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock.
摘要翻译：系统可以包括承载信号的总线，帧脉冲发生器，其生成具有描绘连续定时周期的定时边界的大致周期性帧脉冲信号，以及对于定时边界附近的每个定时周期的一部分有效的帧脉冲使能信号，第一控制缓冲器，在帧脉冲使能信号有效以产生修改的帧脉冲的持续时间期间，在总线上驱动帧脉冲信号，参考时钟控制器经由总线接收经修改的帧脉冲，并产生参考时钟使能信号响应于修改的帧脉冲的存在，产生大致周期性参考时钟信号的参考时钟发生器，以及在参考时钟使能信号有效以产生修改的参考的持续时间期间在总线上驱动参考时钟信号的第二受控缓冲器时钟。

96. 发明申请

US20120151247A1 Dynamic Fault Detection and Repair in a Data Communications Mechanism 有权
标题翻译：数据通信机制中的动态故障检测与修复
公开(公告)号：US20120151247A1
公开(公告)日：2012-06-14
申请号：US13159580
申请日：2011-06-14
申请人： Frank D. Ferraiolo , William R. Kelly , Robert J. Reese , Susan M. Rubow , Michael B. Spear
发明人： Frank D. Ferraiolo , William R. Kelly , Robert J. Reese , Susan M. Rubow , Michael B. Spear
IPC分类号： G06F11/20
CPC分类号： H04L45/28 , H04L1/22 , H04L1/24 , H04L7/0025 , H04L7/0337 , H04L25/14 , H04L45/22 , H04L69/40
摘要： A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.
摘要翻译：多个并行通信线路的通信链路包括至少一个冗余线路。在第一方面，线路一次一个地重新校准，而其他线路携带功能数据。如果检测到故障，故障线路被禁用，其余的已校准线路传输功能数据。在第二方面，在校准期间从异常检测到即将发生的线路故障。在第三方面，通过确定发生每个检测到的错误的逻辑通道，并且将逻辑通道映射到当前携带逻辑车道数据的物理线路，从接收器电路输出检测线路故障。

97. 发明授权

US08175205B2 Clock data recovery circuit capable of generating clock signal synchronized with data signal 失效
标题翻译：时钟数据恢复电路能够产生与数据信号同步的时钟信号
公开(公告)号：US08175205B2
公开(公告)日：2012-05-08
申请号：US12883272
申请日：2010-09-16
申请人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
发明人： Masashi Ishii , Takanori Hirota , Atsuhiko Ishibashi , Yasushi Hayakawa , Takeshi Oshita , Yoshiyuki Ota
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/087
摘要： A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.
摘要翻译：相位比较电路检测数据信号与可变延迟电路的输出之间的相位差。代码运算符检测对应于等于输出时钟的一个周期的延迟的控制代码的值。然后，当控制码根据相位延迟电路的检测结果而改变时，在可变延迟电路的延迟量超过时钟同步期间的输出时钟的一个周期时，控制代码对应于一次等于输出时钟的一个周期的延迟与控制码相加或相减。因此，即使在数据信号和时钟之间存在频率差，也可以在施加相同的时钟相位的同时使数据信号和时钟同步。

98. 发明授权

US08170167B1 System and method for reducing electromagnetic interference and ground bounce in an information communication system by controlling phase of clock signals among a plurality of information communication devices 有权
标题翻译：通过控制多个信息通信装置中的时钟信号的相位来减少信息通信系统中的电磁干扰和地面反弹的系统和方法
公开(公告)号：US08170167B1
公开(公告)日：2012-05-01
申请号：US13042344
申请日：2011-03-07
申请人： Pierte Roo
发明人： Pierte Roo
IPC分类号： H04L7/04
CPC分类号： H04L7/0033 , H03D3/248 , H04L7/0337
摘要： A communication system including a plurality of communication devices configured to operate according to a plurality of communication clock signals, respectively, wherein the plurality of communication clock signals are based on a common reference clock signal. The communication system further includes a phase-locked loop configured to generate an output signal in response to the common reference clock signal, wherein the output signal is in phase lock with the common reference clock signal; a signal division controller configured to generate a divider reset signal in response to a binary select signal; and a divider configured to generate one of the plurality of communication clock signals by performing frequency division of the output signal, wherein the divider reset signal controls a start time of the frequency division.
摘要翻译：一种通信系统，包括多个通信设备，其被配置为分别根据多个通信时钟信号进行操作，其中所述多个通信时钟信号基于公共参考时钟信号。通信系统还包括锁相环，配置为响应于公共参考时钟信号产生输出信号，其中输出信号与公共参考时钟信号同相锁定; 信号分配控制器，被配置为响应于二进制选择信号产生分频器复位信号; 以及分配器，其被配置为通过执行所述输出信号的分频来生成所述多个通信时钟信号中的一个，其中所述分频器复位信号控制所述分频的开始时间。

99. 发明申请

US20120063524A1 SIGNALING SYSTEM WITH ADAPTIVE TIMING CALIBRATION 审中-公开
标题翻译：具有自适应时序校准的信号系统
公开(公告)号：US20120063524A1
公开(公告)日：2012-03-15
申请号：US13301383
申请日：2011-11-21
申请人： Bret G. STOTT , Craig E. HAMPEL , Frederick A. WARE
发明人： Bret G. STOTT , Craig E. HAMPEL , Frederick A. WARE
IPC分类号： H04L7/00 , G06F12/06
CPC分类号： H04L7/0337 , G11C7/04 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1093 , G11C7/1096 , G11C7/20 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03L7/0814 , H04L1/203 , H04L7/0004 , H04L7/0008 , H04L7/0037 , H04L7/0041
摘要： A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.
摘要翻译：公开了一种信令系统。信令系统包括用于接收数据信号和选通信号的第一集成电路（IC）芯片。第一IC包括在由选通信号指示的时间采样数据信号以产生相位误差信息的电路，以及从第一IC器件输出相位误差信息的电路。该系统还包括信令链路和经由信令链路耦合到第一IC芯片的第二IC芯片，以将数据信号和选通信号输出到第一IC芯片。第二IC芯片包括延迟电路，用于通过延迟第一时间间隔的非周期性定时信号和定时控制电路来产生选通信号，以从第一IC芯片接收相位误差信息，并根据相位误差调整第一时间间隔信息。

100. 发明授权

US08121237B2 Signaling system with adaptive timing calibration 有权
标题翻译：具有自适应定时校准的信号系统
公开(公告)号：US08121237B2
公开(公告)日：2012-02-21
申请号：US11384148
申请日：2006-03-16
申请人： Bret G. Stott , Craig E. Hampel , Frederick A. Ware
发明人： Bret G. Stott , Craig E. Hampel , Frederick A. Ware
IPC分类号： H04L7/00 , G11C7/00
CPC分类号： H04L7/0337 , G11C7/04 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1093 , G11C7/1096 , G11C7/20 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03L7/0814 , H04L1/203 , H04L7/0004 , H04L7/0008 , H04L7/0037 , H04L7/0041
摘要： An integrated circuit device includes a delay circuit, sampling circuit and delay control circuit that cooperate to carry out adaptive timing calibration. The delay circuit generates a timing signal by delaying an aperiodic input signal for a first interval. The sampling circuit samples a data signal in response to the timing signal to generate a sequence of data samples, and also samples the data signal in response to a phase-shifted version of the timing signal to generate a sequence of edge samples. The delay control circuit adjusts the first interval based, at least in part, on a phase error indicated by the sequence of data samples and the sequence of edge samples.
摘要翻译：集成电路装置包括延迟电路，采样电路和延迟控制电路，其协调进行自适应定时校准。延迟电路通过延迟第一间隔的非周期性输入信号来产生定时信号。采样电路响应于定时信号对数据信号进行采样以产生数据样本序列，并且还响应于定时信号的相移版本采样数据信号以产生一系列边缘样本。延迟控制电路至少部分地基于由数据样本序列和边缘样本序列指示的相位误差来调整第一间隔。

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