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91. 发明授权

US09055004B2 Scalable low latency multi-protocol networking device 有权
标题翻译：可扩展的低延迟多协议网络设备
公开(公告)号：US09055004B2
公开(公告)日：2015-06-09
申请号：US13767172
申请日：2013-02-14
申请人： Cisco Technology, Inc.
发明人： Thomas J. Edsall , Putu Harry Subagio , Alessandro Fulli , Christopher A. Wildman , Mingzhe Li , Wei-Jen Huang , Chih-Tsung Huang
IPC分类号： H04L12/56 , H04L12/911 , H04L12/741 , H04L29/06 , H04L12/935 , H04L12/947 , H04L12/931 , H04L12/937
CPC分类号： H04L49/25 , H04L29/0653 , H04L43/04 , H04L45/74 , H04L45/745 , H04L47/12 , H04L47/70 , H04L49/251 , H04L49/253 , H04L49/3009 , H04L49/3063 , H04L49/355 , H04L49/9057 , H04L69/22
摘要： A network device receives a packet that includes a plurality of sets of fields. Sets of fields of the packet are parsed and the field sets are evaluated as soon as they are available to determine whether a processing decision can be made on the packet. Additional field sets may be parsed from the packet and obtained in parallel with determining whether a processing decision can be made, but once it is determined that a processing decision can be made, the evaluating of field sets is terminated such that any further field sets of the packet are ignored for purposes of making a processing decision for the packet.
摘要翻译：网络设备接收包括多组字段的分组。对数据包的字段进行解析，并且一旦可用，即可对字段集进行评估，以确定是否可以对数据包进行处理决定。可以从分组中分析附加的字段集，并且与确定是否可以进行处理决定并行获得，但是一旦确定可以进行处理决定，则终止场集合的评估，使得任何另外的字段集合为了对分组进行处理决定，该分组被忽略。

92. 发明授权

US09049153B2 Logical packet processing pipeline that retains state information to effectuate efficient processing of packets 有权
标题翻译：逻辑分组处理流水线保留状态信息以实现分组的高效处理
公开(公告)号：US09049153B2
公开(公告)日：2015-06-02
申请号：US13218464
申请日：2011-08-26
申请人： Martin Casado , Teemu Koponen , Pankaj Thakkar
发明人： Martin Casado , Teemu Koponen , Pankaj Thakkar
IPC分类号： H04L12/26 , H04L12/54 , G06F9/38 , G06F15/16 , H04L12/931 , H04L12/933 , H04L12/713 , H04L12/24 , H04L12/935 , G06F15/173 , G06F11/07
CPC分类号： H04L41/0893 , G06F11/07 , G06F15/17312 , H04L12/4633 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L45/00 , H04L45/586 , H04L47/783 , H04L49/00 , H04L49/1546 , H04L49/3063 , H04L49/70 , H04L61/2007 , H04L61/6022
摘要： Some embodiments provide a method of processing a packet through a logical switching element implemented by several managed switching elements. The method receives a packet for processing through a processing pipeline of the logical switching element. The method processes the packet through the processing pipeline. The method stores state information in the packet for indicating that the packet has been processed through the processing pipeline in order to prevent other managed switching elements from processing the packet through the processing pipeline. The method forwards the processed packet to a managed switching element of the several managed switching elements.
摘要翻译：一些实施例提供了通过由多个管理的交换元件实现的逻辑交换元件来处理分组的方法。该方法通过逻辑交换元件的处理流水线接收处理数据包。该方法通过处理流程处理数据包。该方法将用于指示分组已经通过处理流水线处理的分组中的状态信息存储，以便防止其他被管理的交换单元通过处理流水线处理分组。该方法将处理的分组转发到多个被管理的交换单元的被管理的交换单元。

93. 发明申请

US20150078211A1 SYSTEM AND METHOD FOR HIGH SPEED PACKET TRANSMISSION 有权
标题翻译：用于高速分组传输的系统和方法
公开(公告)号：US20150078211A1
公开(公告)日：2015-03-19
申请号：US14326859
申请日：2014-07-09
申请人： Foundry Networks, LLC
发明人： Yuen Fai Wong
IPC分类号： H04L12/931 , H04L5/14 , H04L12/741 , H04L12/935
CPC分类号： H04L49/352 , H04L5/14 , H04L12/4645 , H04L45/745 , H04L45/7453 , H04L49/30 , H04L49/3063 , H04Q11/0428
摘要： The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.
摘要翻译：本发明提供了用于在一个或多个源设备与一个或多个目的地设备之间提供超过每秒10吉比特的数据传输速度的系统和方法。根据一个实施例，本发明的系统包括第一和第二媒体访问控制（MAC）接口，以便于在相关联的一组物理接口上接收和传输分组。该系统还考虑了耦合到MAC接口和相关联的第一和第二存储器结构的第一和第二现场可编程门阵列（FPGA），第一和第二FPGA被配置为执行从第一和第二MAC接口接收的分组的初始处理并且调度分组到第一和第二MAC接口的传输以传输到一个或多个目的地设备。第一和第二FPGA进一步操作以分派和从第一和第二存储器结构检索数据包。耦合到第一和第二存储器结构和背板的第三FPGA可操作以从第一和第二存储器结构检索和分配分组，计算分组的适当目的地并组织用于传输的分组。第三个FPGA进一步操作以从背板接收和分发分组。

94. 发明授权

US08964598B2 Mesh architectures for managed switching elements 有权
标题翻译：用于托管交换元件的网状架构
公开(公告)号：US08964598B2
公开(公告)日：2015-02-24
申请号：US13219533
申请日：2011-08-26
申请人： Martin Casado , Keith E. Amidon , Teemu Koponen , W. Andrew Lambeth
发明人： Martin Casado , Keith E. Amidon , Teemu Koponen , W. Andrew Lambeth
IPC分类号： H04L12/28 , H04L12/44 , G06F15/16 , G06F15/173 , H04L12/931 , H04L12/24 , G06F11/07
CPC分类号： H04L41/0893 , G06F11/07 , G06F15/17312 , H04L12/4633 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L45/00 , H04L45/586 , H04L47/783 , H04L49/00 , H04L49/1546 , H04L49/3063 , H04L49/70 , H04L61/2007 , H04L61/6022
摘要： Some embodiments provide a network architecture that includes several lower level managed switching elements for forwarding network data to several of network hosts. The network architecture includes a set of higher level managed switching elements. The several lower level managed switching elements and the set of higher level managed switching elements implement several logical datapath sets. Communication channels are established among the several lower level managed switching elements and the set of higher level managed switching elements based on a mesh topology.
摘要翻译：一些实施例提供了一种网络架构，其包括用于将网络数据转发到多个网络主机的多个下级管理交换单元。网络架构包括一组更高级别的托管交换元件。几个较低级别的管理交换元件和一组较高级别的受管交换元件实现了几个逻辑数据路径集。在几个较低级别的管理交换元件和基于网格拓扑的一组较高级别的被管理交换元件之间建立通信信道。

95. 发明申请

US20150019938A1 IN-LINE PACKET PROCESSING 有权
公开(公告)号：US20150019938A1
公开(公告)日：2015-01-15
申请号：US14502399
申请日：2014-09-30
申请人： Juniper Networks, Inc.
发明人： Rasoul Mirzazadeh OSKOUY , Dennis C. FERGUSON , Hann-Hwan Ju , Raymond Marcelino Manese LIM , Pradeep S. SINDHU , Sreeram VEERAGANDHAM , Jeff ZIMMER , Michael M.Y. HUI
IPC分类号： H04L12/741 , H04L29/06 , G06F11/08
CPC分类号： H04L45/74 , G06F11/08 , H04L1/0041 , H04L12/56 , H04L12/5601 , H04L29/06 , H04L45/00 , H04L45/20 , H04L45/60 , H04L47/6225 , H04L49/103 , H04L49/108 , H04L49/203 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/3009 , H04L49/3063 , H04L49/3081 , H04L49/555 , H04L49/602 , H04L49/608 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324 , H04L2012/5652 , H04L2012/5679 , H04Q11/0478
摘要： A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.

96. 发明授权

US08837493B2 Distributed network control apparatus and method 有权
标题翻译：分布式网络控制装置及方法
公开(公告)号：US08837493B2
公开(公告)日：2014-09-16
申请号：US13177534
申请日：2011-07-06
申请人： Martin Casado , Teemu Koponen , W. Andrew Lambeth , Pankaj Thakkar
发明人： Martin Casado , Teemu Koponen , W. Andrew Lambeth , Pankaj Thakkar
IPC分类号： H04L12/28 , H04L12/54 , G06F15/16 , G06F15/173 , H04L12/931 , H04L12/24
CPC分类号： H04L41/0893 , G06F11/07 , G06F15/17312 , H04L12/4633 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L45/00 , H04L45/586 , H04L47/783 , H04L49/00 , H04L49/1546 , H04L49/3063 , H04L49/70 , H04L61/2007 , H04L61/6022
摘要： Some embodiments provide a distributed control system for controlling managed switching elements of a network. The distributed control system comprises a first controller for converting a first set of input logical control plane data to a first set of output logical forwarding plane data. It also includes a second controller for converting a second set of input logical control plane data to a second set of output logical forwarding plane data. The logical forwarding plane data is translated into physical forwarding behaviors that direct the forwarding of data by the managed switching elements.
摘要翻译：一些实施例提供用于控制网络的被管理交换单元的分布式控制系统。分布式控制系统包括用于将第一组输入逻辑控制平面数据转换为第一组输出逻辑转发平面数据的第一控制器。它还包括用于将第二组输入逻辑控制平面数据转换为第二组输出逻辑转发平面数据的第二控制器。逻辑转发平面数据被转换为物理转发行为，其指导被管理交换元件转发数据。

97. 发明申请

US20140050224A1 PROVIDING A BUFFERLESS TRANSPORT METHOD FOR MULTI-DIMENSIONAL MESH TOPOLOGY 审中-公开
标题翻译：提供一种用于多维网格拓扑的无缓冲传输方法
公开(公告)号：US20140050224A1
公开(公告)日：2014-02-20
申请号：US14063858
申请日：2013-10-25
申请人： Michael Kauschke , Gautam B. Doshi
发明人： Michael Kauschke , Gautam B. Doshi
IPC分类号： H04L12/911 , H04L12/863
CPC分类号： H04L47/826 , H04L45/06 , H04L47/50 , H04L49/00 , H04L49/109 , H04L49/1584 , H04L49/3063 , H04L49/90
摘要： In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定在节点的输入/输出（I / O）电路中接收的分组是否发往该节点的方法，如果是，则将分组提供给I / O电路并且确定I / O电路的入口队列中是否存在一个或多个分组，并且如果是，则根据与业务流独立的全局调度将选择的分组提供给第一或第二输出寄存器。描述和要求保护其他实施例。

98. 发明申请

US20130311601A1 HTTP REQUEST PIPELINE OPTIMIZATION 有权
标题翻译： HTTP请求管道优化
公开(公告)号：US20130311601A1
公开(公告)日：2013-11-21
申请号：US13474486
申请日：2012-05-17
申请人： Vivek Sekhar
发明人： Vivek Sekhar
IPC分类号： G06F15/16
CPC分类号： G06F17/30899 , H04L1/0052 , H04L49/1546 , H04L49/3063
摘要： A computing device comprising a transmitter/receiver adapted to communicate with a network and an application adapted to send a plurality of object requests through the transmitter/receiver, wherein, the plurality of object requests are placed in an order dependent upon at least one of an object size and an object type.
摘要翻译：一种计算设备，包括适于与网络通信的发射机/接收机，以及适于通过所述发射机/接收机发送多个对象请求的应用，其中，所述多个对象请求按照依次取决于对象大小和对象类型。

99. 发明授权

US08553686B2 Performing actions on frame entries in response to receiving bulk instruction 失效
标题翻译：响应接收批量指令对帧条目执行操作
公开(公告)号：US08553686B2
公开(公告)日：2013-10-08
申请号：US12769369
申请日：2010-04-28
申请人： Brandon Carl Smith
发明人： Brandon Carl Smith
IPC分类号： H04L12/56
CPC分类号： H04L49/3063 , H04L49/3009
摘要： Various example embodiments are disclosed. According to an example embodiment, a switch may comprise an instruction decode stage and a lookup stage. The instruction decode stage may be configured to receive a bulk instruction identifying an action to perform on frame entries of the lookup stage, and in response to receiving the bulk instruction, send, to the lookup stage, at least first and second frame entry instructions, each of the first and second frame entry instructions identifying the action and identifying a unique frame entry in the lookup stage upon which to perform the action. The lookup stage may be configured to receive the first and second frame entry instructions from the instruction decode stage, and in response to receiving each of the first and second frame entry instructions, perform the identified action on the frame entry identified by the respective frame entry instruction.
摘要翻译：公开了各种示例性实施例。根据示例实施例，交换机可以包括指令解码级和查找级。指令解码级可以被配置为接收标识要在查找级的帧条目上执行的动作的批量指令，并且响应于接收批量指令，向查找级发送至少第一和第二帧入口指令，所述第一和第二帧入口指令中的每一个标识所述动作，并且在所述查找阶段中标识执行所述动作的唯一帧条目。查找阶段可以被配置为从指令解码级接收第一和第二帧入口指令，并且响应于接收到第一和第二帧入口指令中的每一个，对由相应帧条目标识的帧条目执行所识别的动作指令。

100. 发明授权

US08477780B2 Processing packet information using an array of processing elements 有权
标题翻译：使用一系列处理元素处理数据包信息
公开(公告)号：US08477780B2
公开(公告)日：2013-07-02
申请号：US10809164
申请日：2004-03-25
申请人： Robert J. Schultz
发明人： Robert J. Schultz
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/3009 , H04L49/3063 , H04L49/40
摘要： Processing packet information using an array of processing elements involves performing search-independent processing on packet information in parallel with a search of a first stage memory unit and then using the processed information and the result from the search of the first stage memory unit to generate search information for a search of a second stage memory unit. The search-independent processing of packet information in parallel with search operations can be repeated at each stage of the array. By performing search-independent processing of packet information in parallel with search operations instead of serially, latency that is contributed from the relatively slow search operations is reduced.
摘要翻译：使用处理单元阵列处理分组信息涉及对第一级存储器单元的搜索并行地对分组信息进行搜索独立处理，然后使用经处理的信息和来自第一级存储器单元的搜索的结果来生成搜索用于搜索第二级存储器单元的信息。与搜索操作并行的分组信息的搜索独立处理可以在阵列的每个阶段重复。通过与搜索操作并行地执行分组信息的搜索独立处理而不是串行地执行，从相对较慢的搜索操作中贡献的等待时间减少。

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