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91. 发明授权

US09450610B1 High quality log likelihood ratios determined using two-index look-up table 有权
标题翻译：使用双索引查找表确定高质量对数似然比
公开(公告)号：US09450610B1
公开(公告)日：2016-09-20
申请号：US14557214
申请日：2014-12-01
申请人： Microsemi Storage Solutions (US), Inc.
发明人： Rino Micheloni , Alessia Marelli , Christopher I. W. Norrie
IPC分类号： H03M13/00 , H03M13/11 , G06F11/10
CPC分类号： H03M13/1125 , G06F11/1012 , G06F11/1048 , G06F11/1072 , H03M13/1108 , H03M13/1111 , H03M13/3723
摘要： A nonvolatile memory controller includes memory storage configured to store a two-index look-up table that includes a Log-Likelihood Ratio (LLR), hard-and-soft-decision bits associate with the LLR and a neighboring cell read pattern associated with the LLR. Read circuitry is configured to perform a plurality of reads of a cell of a nonvolatile memory storage module at different read voltage levels to generate target cell hard-and-soft-decision bits and configured to read neighboring cells to generate neighboring cell reads. Neighboring cell processing circuitry combines the neighboring cell reads to generate a neighboring cell read pattern. Look-up circuitry accesses the two-index look-up table using the target cell hard-and-soft-decision bits and the neighboring cell read pattern to identify the corresponding LLR for use in Low-Density Parity Check (LDPC) decoding of a codeword stored in the nonvolatile memory storage module.
摘要翻译：非易失性存储器控制器包括被配置为存储双索引查找表的存储器存储器，其包括对数似然比（LLR），与LLR相关联的硬和软判决位以及与该LLR相关联的相邻单元读取模式 LLR。读取电路被配置为以不同的读取电压电平执行非易失性存储器存储模块的单元的多个读取，以生成目标单元硬和软判决位，并且被配置为读取相邻单元以产生相邻单元读取。相邻小区处理电路组合相邻小区读取以生成相邻小区读取模式。查找电路使用目标单元硬和软判决位和相邻单元读取模式来访问双索引查找表，以识别在低密度奇偶校验（LDPC）解码中使用的相应LLR。存储在非易失性存储器存储模块中的码字。

92. 发明授权

US09436549B2 Storage module and method for improved error correction by detection of grown bad bit lines 有权
标题翻译：存储模块和方法，用于通过检测生长的坏位线来改进纠错
公开(公告)号：US09436549B2
公开(公告)日：2016-09-06
申请号：US14502738
申请日：2014-09-30
申请人： SanDisk Technologies Inc.
发明人： Daniel E. Tuers , Abjiheet Manohar
IPC分类号： G06F11/10 , G06F11/07 , H03M13/11 , H03M13/03 , H03M13/37 , G11C16/26 , H03M13/15 , H03M13/45 , H03M13/00
CPC分类号： G06F11/1076 , G06F11/1012 , G11C29/025 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C2029/0403 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208 , G11C2029/4402 , H03M13/1102 , H03M13/1111 , H03M13/152 , H03M13/3723 , H03M13/451 , H03M13/6325
摘要： In one embodiment, a storage module comprises a controller and a memory having a plurality of bit lines. The controller detects an uncorrectable error in a code word read from the memory, determines location(s) of grown bad bit line(s) that contributed to the error in the code word being uncorrectable, and uses the determined location(s) of the grown bad bit line(s) to attempt to correct the error in the code word.
摘要翻译：在一个实施例中，存储模块包括控制器和具有多个位线的存储器。控制器检测从存储器读取的代码字中的不可校正错误，确定有助于代码字中的错误是不可校正的生长坏位线的位置，并使用确定的位置生成坏的位线来尝试纠正代码字中的错误。

93. 发明授权

US09391638B1 Error indications in error correction code (ECC) protected memory systems 有权
标题翻译：纠错码（ECC）保护的存储器系统中的错误指示
公开(公告)号：US09391638B1
公开(公告)日：2016-07-12
申请号：US13670628
申请日：2012-11-07
申请人： Marvell Israel (M.I.S.L.) Ltd.
发明人： Assaf Metuki
IPC分类号： H03M13/00 , H03M13/11 , H03M13/09 , G06F11/10 , H04L1/00
CPC分类号： H03M13/11 , G06F11/1012 , G06F11/1056 , H03M13/09 , H03M13/19 , H03M13/3723 , H04L1/0041 , H04L1/0057 , H04L1/0061 , H04L1/0082
摘要： Some of the embodiments of the present disclosure provide a method including receiving data to be stored in a memory, the data including (i) data bits and (ii) a tag indicating that one or more of the data bits are corrupted; generating eight error correction code (ECC) bits corresponding to the data bits of the data; in response to the data including the tag indicating that one or more of the data bits are corrupted, modifying seven bits of the eight ECC bits to generate modified ECC bits, wherein the seven bits of the eight ECC bits are modified to indicate that one or more of the corresponding data bits are corrupted; and writing the data bits, along with the modified ECC bits, to the memory. Other embodiments are also described and claimed.
摘要翻译：本公开的一些实施例提供了一种包括接收要存储在存储器中的数据的方法，所述数据包括（i）数据位和（ii）指示一个或多个数据位被破坏的标签; 产生与数据的数据位相对应的八个纠错码（ECC）位; 响应于包括指示一个或多个数据位被损坏的标签的数据，修改八个ECC位的七位以产生修改的ECC位，其中八个ECC位的七位被修改以指示一个或更多的相应的数据位被破坏; 并将数据位与修改的ECC位一起写入存储器。还描述和要求保护其他实施例。

94. 发明申请

US20160173229A1 METHOD AND DEVICE FOR RECEIVING SIGNALS IN WIRELESS ACCESS SYSTEM 审中-公开
标题翻译：用于在无线接入系统中接收信号的方法和装置
公开(公告)号：US20160173229A1
公开(公告)日：2016-06-16
申请号：US14902771
申请日：2014-08-05
申请人： LG ELECTRONICS INC.
发明人： Kwangseok NOH , Jinmin KIM , Kukheon CHOI , Jaehoon CHUNG , Kitae KIM
IPC分类号： H04L1/00 , H03M13/11 , H03M13/29 , H04W72/08 , H04L5/00
CPC分类号： H04L1/0045 , H03M13/1102 , H03M13/1111 , H03M13/2909 , H03M13/3723 , H03M13/612 , H03M13/658 , H04L1/0057 , H04L1/06 , H04L5/001 , H04L5/006 , H04W72/085 , H04W88/02
摘要： The present invention relates to a method for receiving signals in a wireless communication system. A method by which a terminal receives signals in a wireless communication system, according to one embodiment of the present invention, can comprise the steps of: receiving N signals through N channels; and decoding the N signals by using a low density parity check (LDPC) sum-product channel decoder, wherein a first weight value is applied to a variable node of the LDPC sum-product channel decoder, a second weight value is applied to a reception signal node thereof, and the first weight value is less than 1 for channels of which a channel state has a reference value or less among the N channels.
摘要翻译：本发明涉及一种在无线通信系统中接收信号的方法。根据本发明的一个实施例，终端在无线通信系统中接收信号的方法可以包括以下步骤：通过N个信道接收N个信号; 以及通过使用低密度奇偶校验（LDPC）和乘积信道解码器对N个信号进行解码，其中第一加权值被施加到LDPC和乘积信道解码器的可变节点，第二加权值被应用于接收信道节点，并且对于信道状态在N个信道中具有参考值或更小的信道，第一加权值小于1。

95. 发明授权

US09367246B2 Performance optimization of data transfer for soft information generation 有权
标题翻译：软信息生成的数据传输性能优化
公开(公告)号：US09367246B2
公开(公告)日：2016-06-14
申请号：US13963444
申请日：2013-08-09
申请人： SanDisk Enterprise IP LLC
发明人： Jack Edward Frayer , Aaron K. Olbrich
IPC分类号： G06F3/00 , G06F3/06 , G06F11/10 , H03M13/37 , H03M13/45
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/068 , G06F11/1048 , H03M13/3723 , H03M13/3769 , H03M13/45
摘要： A single command initiates a first read operation and sequence of one or more additional read operations from the same portion of memory. The one or more additional read operations are terminable after the first read operation provides a first plurality of data values that is made available to a requesting device and/or module. In some implementations, the first plurality of data values includes hard information values. Subsequent pluralities of data values are generated from the same portion of memory until a terminating event occurs. In some implementations, until a terminating event occurs, a respective hybrid plurality of data values is generated by combining the latest read plurality of data values with one of a previously generated hybrid plurality of data values and the first plurality of data values. Each hybrid plurality of data values is representative of a corresponding plurality of soft information values.
摘要翻译：单个命令从存储器的相同部分启动一个或多个附加读取操作的第一读取操作和序列。在第一读取操作提供使得可用于请求设备和/或模块的第一多个数据值之后，一个或多个附加读取操作可终止。在一些实现中，第一多个数据值包括硬信息值。后续的多个数据值从存储器的相同部分生成直到发生终止事件。在一些实现中，直到发生终止事件，通过将最新读取的多个数据值与先前产生的混合多个数据值和第一多个数据值中的一个组合来生成相应的混合多个数据值。每个混合多个数据值表示相应的多个软信息值。

96. 发明授权

US09337867B2 Cyclic decoding for cascaded forward error-correction FEC codes 有权
标题翻译：用于级联前向纠错FEC码的循环解码
公开(公告)号：US09337867B2
公开(公告)日：2016-05-10
申请号：US14249609
申请日：2014-04-10
申请人： NEC Laboratories America, Inc.
发明人： Shaoliang Zhang , Fatih Yaman , Yequn Zhang
IPC分类号： H03M13/11 , H03M13/35 , H03M13/37 , H03M13/39
CPC分类号： H03M13/1111 , H03M13/1145 , H03M13/353 , H03M13/3723 , H03M13/3746 , H03M13/3776 , H03M13/3905 , H03M13/3972
摘要： A computer implemented method for a cyclic (forward-backward) decoding for a forward error-correction FEC scheme includes decoding a given k−1th codeword in a block code of length N in an optical communication system, forwarding M symbols' enhanced log likelihood ratios LLRs produced by decoding the k−1th codeword, decoding the kth codeword together with forwarded M symbols' enhanced LLRS, and feeding backward, to the initial step i) decoding, corresponding overlapped M symbols' enhanced LLRs for decoding of the k−1th codeword again.
摘要翻译：用于前向纠错FEC方案的循环（前向 - 反向）解码的计算机实现方法包括在光通信系统中解码长度为N的块码中的给定k-1个码字，将M个符号的增强对数似然比通过解码第k-1个码字产生的LLR，将第k个码字与转发的M个符号的增强的LLRS一起解码，并向后馈送到初始步骤i）解码对应的重叠的M个符号的增强的LLR用于第k-1个码字的解码再次。

97. 发明授权

US09323606B2 Systems and methods for FAID follower decoding 有权
标题翻译： FAID跟随器解码的系统和方法
公开(公告)号：US09323606B2
公开(公告)日：2016-04-26
申请号：US14101368
申请日：2013-12-10
申请人： LSI Corporation
发明人： Yequn Zhang , Yang Han , Yu Chin Fabian Lim , Shu Li , Fan Zhang , Shaohua Yang
IPC分类号： H03M13/00 , G06F11/10 , H03M13/09 , H03M13/11 , H03M13/27 , H03M13/29 , H03M13/37 , H03M13/41
CPC分类号： G06F11/1008 , G06F11/10 , H03M13/09 , H03M13/1111 , H03M13/27 , H03M13/2957 , H03M13/3707 , H03M13/3723 , H03M13/3746 , H03M13/41 , H03M13/6331 , H03M13/6343 , H03M13/6594
摘要： Systems and method relating generally to data processing, and more particularly to systems and methods for decoding information. Some disclosed systems include a first data decoding circuit, a second data decoding circuit, and a data output circuit. The second data decoding circuit is coupled to the first data decoding circuit and the data output circuit. The second data decoding circuit is operable to apply a finite alphabet iterative decoding algorithm to the first decoded output to yield a second decoded output.
摘要翻译：一般涉及数据处理的系统和方法，更具体地涉及用于解码信息的系统和方法。一些公开的系统包括第一数据解码电路，第二数据解码电路和数据输出电路。第二数据解码电路耦合到第一数据解码电路和数据输出电路。第二数据解码电路可操作以将有限字母迭代解码算法应用于第一解码输出以产生第二解码输出。

98. 发明授权

US09298547B2 Detection/erasure of random write errors using converged hard decisions 有权
标题翻译：使用融合硬判决来检测/擦除随机写入错误
公开(公告)号：US09298547B2
公开(公告)日：2016-03-29
申请号：US14150810
申请日：2014-01-09
申请人： LSI Corporation
发明人： Abdel-Hakim S. Alhussien , Erich F. Haratsch , Yunxiang Wu
IPC分类号： G06F11/10 , G11C29/52 , G11C29/42 , G11C29/56 , G11C29/04 , H03M13/37 , H03M13/11 , H03M13/45 , G11C29/50 , G11C11/56
CPC分类号： G06F11/1072 , G06F11/1012 , G11C11/56 , G11C29/42 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004 , H03M13/1105 , H03M13/1142 , H03M13/3723 , H03M13/373 , H03M13/3769 , H03M13/451
摘要： A low-density parity-check decoder in a system with multi-level cells identifies zones of reliability where write errors or stuck cells are identifiable. The system uses assumedly successfully decoded pages associated with bits in a cell to identify candidate write errors or stuck cells and erases a corresponding log-likelihood ratio even where such log-likelihood ratio is saturated, thereby breaking a potential trapping set without post-processing.
摘要翻译：具有多级单元的系统中的低密度奇偶校验解码器识别写入错误或被卡住的单元是可识别的可靠性区域。该系统使用与单元中的位相关联的假设成功解码的页面来识别候选写入错误或卡住的单元并且擦除相应的对数似然比，即使这样的对数似然比饱和，从而破坏潜在的陷阱集而不进行后处理。

99. 发明申请

US20160077914A1 SOLID STATE STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF 审中-公开
标题翻译：固态存储器件及其错误校正方法
公开(公告)号：US20160077914A1
公开(公告)日：2016-03-17
申请号：US14644656
申请日：2015-03-11
申请人： LITE-ON TECHNOLOGY CORPORATION
发明人： Shih-Jia Zeng , Sheng-Han Wu , Jen-Chien Fu , Yu-Shan Wu
IPC分类号： G06F11/10 , H03M13/11 , H03M13/45 , G11C29/52
CPC分类号： G06F11/1012 , G11C29/021 , G11C29/028 , G11C2029/0411 , H03M13/1108 , H03M13/1148 , H03M13/3723 , H03M13/45 , H03M13/451 , H03M13/6325
摘要： An error correction method for a solid state storage device is provided. A controller of the solid state storage device issues plural slicing voltages to a flash memory. The flash memory issues a soft data to a soft decoder of the controller according to the plural slicing voltages. Firstly, the soft decoder receives the soft data, and performs an error correction process of the soft data according to a predetermined log-likelihood ratio (LLR) parameter set. If the error correction process of the soft data is not successfully completed according to the predetermined LLR parameter set, one LLR parameter set is selected from plural parameter sets of a LLR table and the error correction process of the soft data is performed according to the selected LLR parameter set.
摘要翻译：提供了一种固态存储装置的纠错方法。固态存储装置的控制器向闪存发出多个切片电压。闪存根据多个切片电压将软数据发送到控制器的软解码器。首先，软解码器接收软数据，并根据预定的对数似然比（LLR）参数集进行软数据的纠错处理。如果软数据的纠错处理根据预定的LLR参数组未成功完成，则从LLR表的多个参数组中选择一个LLR参数集，并根据所选择的执行软数据的纠错处理 LLR参数集。

100. 发明申请

US20160006462A1 NON-VOLATILE MEMORY CONTROLLER WITH ERROR CORRECTION (ECC) TUNING VIA ERROR STATISTICS COLLECTION 有权
标题翻译：具有错误校正（ECC）的非易失性存储器控制器通过错误统计信息收集
公开(公告)号：US20160006462A1
公开(公告)日：2016-01-07
申请号：US14325244
申请日：2014-07-07
申请人： OCZ Storage Solutions, Inc.
发明人： Paul Edward HANHAM , David Malcolm SYMONS , Neil BUXTON
IPC分类号： H03M13/37 , H03M13/45 , H03M13/11 , G06F11/10 , G11C29/52
CPC分类号： H03M13/3715 , G06F11/1012 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3723 , H03M13/458 , H03M13/6325
摘要： A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance.
摘要翻译：用于固态驱动器的非易失性存储器控制器包括软判决LDPC解码器。软判决LDPC解码器包括概率生成模块。处理器从解码帧读取收集的统计信息，并调整软判决LDPC解码器性能的性能。还可以考虑附加参数，例如加扰种子和非易失性存储器的类型。还可以检测错误的不对称性并将其提供给硬判决LDPC解码器以调整其性能。

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