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91. 发明申请

US20140136918A1 RECONSTRUCTIVE ERROR RECOVERY PROCEDURE (ERP) USING RESERVED BUFFER 有权
标题翻译：重建错误恢复程序（ERP）使用保留缓冲区
公开(公告)号：US20140136918A1
公开(公告)日：2014-05-15
申请号：US13676477
申请日：2012-11-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Takashi Katagiri , Pamela R. Nylander-Hill
IPC分类号： H03M13/29
CPC分类号： H03M13/2906 , G11B20/1833 , G11B2020/1853 , H03M13/2909 , H03M13/293 , H03M13/3715
摘要： According to one embodiment, a method for reading data from a medium includes reading a data set from a medium repeatedly using different settings until either: a reconstructed data set is sent to a host and/or stored, or a maximum number of rereads has been reached, after each reading of the data set, storing each row to the reserved data buffer that has no errors or errors in the row are correctable using C1-Error Correction Code (ECC) unless a matching row already exists in the reserved data buffer that has fewer corrected errors therein, assembling the data set from the rows stored in the reserved data buffer to form an assembled data set, correcting any remaining errors in the assembled data set using C2-ECC to form the reconstructed data set, and sending the reconstructed data set to the host and/or storing the reconstructed data set.
摘要翻译：根据一个实施例，一种用于从介质读取数据的方法包括：使用不同的设置从介质重复读取数据集，直到：将重建的数据集发送到主机和/或存储，或者最大数量的重读已被在每次读取数据集之后，将每一行存储到不存在错误或错误的保留数据缓冲器中，可以使用C1错误校正码（ECC）进行校正，除非在保留的数据缓冲器中已经存在匹配的行，在其中具有较少的校正误差，从存储在保留数据缓冲器中的行组合数据集以形成组合数据集，使用C2-ECC校正组合数据集中的任何剩余错误，以形成重构数据集，并发送重建的数据设置到主机和/或存储重建的数据集。

92. 发明授权

US08700972B2 Adaptive ultra-low voltage memory 有权
标题翻译：自适应超低电压存储器
公开(公告)号：US08700972B2
公开(公告)日：2014-04-15
申请号：US13289691
申请日：2011-11-04
申请人： Paul Penzes , Mark Fullerton , Ajat Hukkoo , John Walley
发明人： Paul Penzes , Mark Fullerton , Ajat Hukkoo , John Walley
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3296 , G06F11/1064 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , H03M13/19 , H03M13/3715 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).
摘要翻译：实施例提供允许低电压操作模式的自适应存储器。在低电压工作模式下，提供给存储器的电源电压降至低于Vcc（min），这样可以显着节省最小电压由Vcc（min）决定的电路组件（例如CPU）的功耗）。根据另外的实施例，可以根据期望的功率节省（例如，目标Vcc（min））和/或性能要求（例如，可靠性，高速缓存大小要求等）根据各种配置来动态地配置存储器。

93. 发明授权

US08694858B2 Memory controller and operating method of memory controller 有权
标题翻译：内存控制器和内存控制器的操作方法
公开(公告)号：US08694858B2
公开(公告)日：2014-04-08
申请号：US13467497
申请日：2012-05-09
申请人： JaePhil Kong , Yongwon Cho
发明人： JaePhil Kong , Yongwon Cho
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： H03M13/1545 , G06F1/3225 , G06F1/3275 , G06F11/1048 , H03M13/09 , H03M13/152 , H03M13/3715 , Y02D10/13 , Y02D10/14
摘要： A controller to control a memory system including a memory device. The controlling the memory system may include calculating an error location polynomial in a received read vector with a key equation solving unit of the memory system to read data from the memory device, estimating the number of errors in the received read vector with a control unit of the memory system according to at least one of the calculated error location polynomial and information on the error location polynomial, searching error locations of the received read vector according to the calculated error location polynomial with a chien search unit of the memory system with the control unit. A cycle-per power consumption of the chien search unit may be adjusted with the control unit. A maximum correction time may be adjusted according to the number of errors of the read vector.
摘要翻译：一种用于控制包括存储器件的存储器系统的控制器。控制存储器系统可以包括利用存储器系统的密钥方程求解单元来计算接收到的读取向量中的误差位置多项式以从存储器件读取数据，使用控制单元估计所接收的读取向量中的错误数所述存储器系统根据计算出的错误位置多项式和关于错误位置多项式的信息中的至少一个，根据所计算的误差位置多项式与存储器系统的chien搜索单元与控制单元搜索错误位置。可以通过控制单元来调整chien搜索单元的每个功率消耗周期。可以根据读取向量的错误数来调整最大校正时间。

94. 发明申请

US20140082455A1 DECODING DEVICE 有权
标题翻译：解码设备
公开(公告)号：US20140082455A1
公开(公告)日：2014-03-20
申请号：US14110697
申请日：2013-03-05
申请人： PANASONIC CORPORATION
发明人： Naoya Yosoku , Hiroyuki Yoshikawa , Hiroyuki Motozuka
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , H03M13/1117 , H03M13/1137 , H03M13/3715 , H03M13/6527 , H03M13/6577 , H03M13/658
摘要： A decoding device has a decoding section that has a plurality of decoding cores which decode a received packet (e.g., likelihoods generated as a result of demodulation), which will become data to be decoded, in parallel on a per-likelihood basis and in which a first decoding core and a second decoding core of a plurality of decoding cores can perform decoding in parallel and a control section that controls decoding, wherein the decoding section lets the second decoding core decode a second likelihood when the second likelihood is input in the middle of the first decoding core decoding the first likelihood of the data to be decoded, whereby another likelihood can be decoded by use of another decoding core in the middle of decoding of a certain likelihood. Thus, entire decoding speed is increased.
摘要翻译：解码装置具有解码部分，其具有多个解码核，其解码接收的分组（例如，作为解调结果生成的似然性），其将成为将被解码的数据，并且基于每个可能性，并且其中多个解码核心的第一解码核心和第二解码核心可以并行地执行解码，以及控制解码部分，其中当第二可能性在中间输入时，解码部分使第二解码核心解码第二似然第一解码核心解码要解码的数据的第一可能性，从而在某种可能性的解码的中间通过使用另一个解码核心来解码另一似然。因此，整个解码速度增加。

95. 发明授权

US08677222B2 Method and device for decoding Reed-Solomon (RS) code 有权
标题翻译：用于解码里德 - 所罗门（RS）代码的方法和设备
公开(公告)号：US08677222B2
公开(公告)日：2014-03-18
申请号：US13258449
申请日：2010-05-04
申请人： Yueyi You , Qiang Li , Ning Qiu , Nanshan Cao , Tao Zhang
发明人： Yueyi You , Qiang Li , Ning Qiu , Nanshan Cao , Tao Zhang
IPC分类号： H03M13/00
CPC分类号： H03M13/1515 , H03M13/3715 , H03M13/451 , H03M13/458 , H03M13/616
摘要： The embodiments of the invention disclose a method and a device for decoding an RS code, the method comprising: receiving bit reliability information of the RS code output by a channel, performing a hard decision on the bit reliability information to obtain a hard-decision result value sequence; determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code; according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode; outputting the hard-decision result value sequence after the bit error correction as a decoding result.
摘要翻译：本发明的实施例公开了一种用于对RS码进行解码的方法和装置，该方法包括：接收由信道输出的RS码的比特可靠性信息，对比特可靠性信息进行硬判决以获得硬判决结果价值序列根据与RS码的编码模式相对应的初始检查阵列，确定硬判决结果值序列的错误的类型; 根据硬判决结果值序列的错误类型和能够校正错误的纠错模式之间的预设对应关系，确定与硬判定结果值序列的错误类型对应的纠错模式，以及根据所确定的纠错模式对所述硬判定结果值序列进行位纠错; 在比特纠错之后输出硬判决结果值序列作为解码结果。

96. 发明授权

US08667378B2 Decoding method and device for concatenated code 有权
标题翻译：连接代码的解码方法和设备
公开(公告)号：US08667378B2
公开(公告)日：2014-03-04
申请号：US13512196
申请日：2010-10-22
申请人： Tao Zhang , Yueyi You , Nanshan Cao , Yangzhong Yao
发明人： Tao Zhang , Yueyi You , Nanshan Cao , Yangzhong Yao
IPC分类号： H03M13/00 , H03M13/03 , G06F11/00
CPC分类号： H03M13/2906 , H03M13/1102 , H03M13/1128 , H03M13/1515 , H03M13/3715 , H03M13/373
摘要： Disclosed are a decoding method and device for concatenated code, for the decoding of concatenated code composed of low density parity code (LDPC) and Reed-Solomon (RS) code. The method includes carrying out LDPC soft decision iterative decoding on bit de-interleaved data flow, and carrying out check decision on LDPC codeword obtained from decoding by using a check matrix; carrying out de-byte-interleave on an information bit of the LDPC codeword obtained from decoding and converting check information of the LDPC codeword into puncturing information of RS codeword; selecting a decoding mode according to the puncturing information of the RS codeword to carry out RS decoding. By way of the solution of the present invention, the RS decoding performance can be improved without increasing the computation complexity, thus greatly improving the receiving performance of the CMMB terminal as compared to the conventional method.
摘要翻译：公开了一种用于级联码的解码方法和装置，用于解码由低密度奇偶码（LDPC）和里德 - 所罗门（RS）码组成的级联码。该方法包括对比特解交织数据流执行LDPC软判决迭代解码，并通过使用校验矩阵对从解码获得的LDPC码进行校验决定; 在从解码获得的LDPC码字的信息比特上进行去字节交织，并将LDPC码字的检查信息转换成RS码字的删截信息; 根据RS码字的删截信息选择解码模式，进行RS解码。通过本发明的解决方案，可以在不增加计算复杂度的情况下提高RS解码性能，从而与常规方法相比大大提高了CMMB终端的接收性能。

97. 发明申请

US20130294550A1 DECODERS AND METHODS FOR DECODING CONVOLUTIONAL CODED DATA 失效
标题翻译：解码转换数据的解码器和方法
公开(公告)号：US20130294550A1
公开(公告)日：2013-11-07
申请号：US13464667
申请日：2012-05-04
申请人： Divaydeep Sikri
发明人： Divaydeep Sikri
IPC分类号： H03M13/23 , G06F11/10 , H04B1/06
CPC分类号： H03M13/23 , H03M13/09 , H03M13/3715 , H03M13/373 , H03M13/3776 , H03M13/41
摘要： Decoder and communications devices including such decoders can obtain a convolutional coded bit stream including a plurality of coded data bits. According to some implementations, if a signal quality associated with the convolutional coded bit stream is above a predetermined threshold, a decoded value for each information bit may be calculated at least from a modulo 2 sum of a coded data bit added to at least one other coded data bit, at least one previously calculated information bit, or a combination of at least one other coded data bit and at least one previously calculated information bit. Also, according to some implementations, if the signal quality associated with the convolutional coded bit stream is not above the predetermined threshold, the convolutional coded bit stream may be decoded with a conventional convolutional decoding scheme. Other aspects, embodiments, and features are also claimed and described.
摘要翻译：包括这种解码器的解码器和通信设备可以获得包括多个编码数据位的卷积编码比特流。根据一些实施方式，如果与卷积编码比特流相关联的信号质量高于预定阈值，则可以至少从加到至少另一个的编码数据比特的模2之和来计算每个信息比特的解码值至少一个先前计算的信息位，或至少一个其它编码数据位和至少一个先前计算的信息位的组合。此外，根据一些实施方式，如果与卷积编码比特流相关联的信号质量不高于预定阈值，则可以用常规卷积解码方案对卷积编码比特流进行解码。还要求和描述其它方面，实施例和特征。

98. 发明授权

US08533576B1 Data independent error computation and usage with decision directed error computation 有权
标题翻译：数据独立的误差计算和使用与决策定向误差计算
公开(公告)号：US08533576B1
公开(公告)日：2013-09-10
申请号：US13012640
申请日：2011-01-24
申请人： Zheng Wu , Jason Bellorado , Marcus Marrow
发明人： Zheng Wu , Jason Bellorado , Marcus Marrow
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H04L1/0041 , G06F11/00 , H03G3/3052 , H03M13/1102 , H03M13/1515 , H03M13/3715 , H04L1/20
摘要： A signal error is determined by obtaining a known property of an expected signal. A signal is received and a signal error is determined based at least in part on the received signal and the known property of the expected signal.
摘要翻译：通过获得预期信号的已知属性来确定信号误差。接收信号并且至少部分地基于接收到的信号和预期信号的已知属性确定信号误差。

99. 发明申请

US20130117626A1 Adaptive Ultra-Low Voltage Memory 有权
标题翻译：自适应超低电压存储器
公开(公告)号：US20130117626A1
公开(公告)日：2013-05-09
申请号：US13289691
申请日：2011-11-04
申请人： Paul PENZES , Mark Fullerton , Ajat Hukkoo , John Walley
发明人： Paul PENZES , Mark Fullerton , Ajat Hukkoo , John Walley
IPC分类号： H03M13/09 , G06F11/10 , G06F1/26
CPC分类号： G06F1/3275 , G06F1/3206 , G06F1/3296 , G06F11/1064 , G06F12/0864 , G06F2212/1028 , G06F2212/601 , H03M13/19 , H03M13/3715 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).
摘要翻译：实施例提供允许低电压操作模式的自适应存储器。在低电压工作模式下，提供给存储器的电源电压降至低于Vcc（min），这样可以显着节省最小电压由Vcc（min）决定的电路组件（例如CPU）的功耗）。根据另外的实施例，可以根据期望的功率节省（例如，目标Vcc（min））和/或性能要求（例如，可靠性，高速缓存大小要求等）根据各种配置来动态地配置存储器。

100. 发明申请

US20130097475A1 LDPC Decoder With Targeted Symbol Flipping 有权
标题翻译：具有目标符号翻转的LDPC解码器
公开(公告)号：US20130097475A1
公开(公告)日：2013-04-18
申请号：US13274443
申请日：2011-10-17
申请人： Chung-Li Wang , Zongwang Li , Shaohua Yang
发明人： Chung-Li Wang , Zongwang Li , Shaohua Yang
IPC分类号： G06F11/08
CPC分类号： H03M13/1108 , H03M13/1117 , H03M13/1171 , H03M13/3715
摘要： Various embodiments of the present invention provide systems and methods for decoding data in a non-binary LDPC decoder with targeted symbol flipping. For example, a non-binary low density parity check data decoder is disclosed that comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.
摘要翻译：本发明的各种实施例提供用于在具有目标符号翻转的非二进制LDPC解码器中解码数据的系统和方法。例如，公开了一种非二进制低密度奇偶校验数据解码器，其包括可变节点处理器，其可操作以根据非二进制伽罗瓦域中的多个元素更新可变节点符号值，校验节点处理器连接到变量并且可操作以执行奇偶校验计算，以及可操作以执行符号翻转并控制可变节点处理器和校验节点处理器中的解码迭代的控制器。

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