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91. 发明授权

US06964005B2 System and method for interleaving data in a communication device 失效
标题翻译：用于在通信设备中交织数据的系统和方法
公开(公告)号：US06964005B2
公开(公告)日：2005-11-08
申请号：US10162062
申请日：2002-06-05
申请人： Scott Hollums
发明人： Scott Hollums
IPC分类号： H03M13/27 , H04L1/00 , H03M13/00
CPC分类号： H04L1/0071 , G06F11/1008 , G06F11/1076 , H03M13/2707 , H03M13/2785 , H03M13/2789 , H04L1/0043 , H04L1/0057 , H04L1/0075 , H04L2001/0094
摘要： A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is also configured to provide control information to the read logic. The control information includes a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information also includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information also includes the byte length size of the burst. The read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information. A block available signal and a block out signal is also provided to determine when a block of data is available to be read from the memory.
摘要翻译：提供了一种用于在通信设备中交织数据的系统和方法。该系统包括存储要被交织的数据块的存储器。除了存储器之外，系统还包括写入模块和读取模块，每个读取模块都耦合到存储器。写入模块被配置为从脉冲串中接收数据的突发数据和写入数据块到存储器中。写模块还被配置为向读逻辑提供控制信息。控制信息包括每个块的滚动突发计数器和突发配置文件组标识符。如果交织被激活，则控制信息还包括与读取模块如何交错块有关的信息。如果未激活交织，则控制信息还包括突发的字节长度大小。读取模块根据控制信息以交错方式或非交错方式从存储器读取数据块。还提供块可用信号和块输出信号以确定数据块何时可用于从存储器读取。

92. 发明申请

US20050154963A1 Deinterleaving device for digital broadcast receivers having a downsized deinterleaver memory and deinterleaving method thereof 失效
标题翻译：具有小型解交织器存储器及其去交织方法的数字广播接收机的解交织装置
公开(公告)号：US20050154963A1
公开(公告)日：2005-07-14
申请号：US10971163
申请日：2004-10-25
申请人： Jeong-taek Lee
发明人： Jeong-taek Lee
IPC分类号： H04N7/01 , H04H40/18 , H03M13/00 , G11C29/00
CPC分类号： H04H40/18 , H03M13/2732 , H03M13/276 , H03M13/2782 , H03M13/2785 , H04H20/426 , H04H2201/20
摘要： Disclosed is a deinterleaving device and method for digital broadcast receivers having a downsized deinterleaver memory. The deinterleaving device includes a memory having storage space for performing the deinterleaving in a number of deinterleaving units over the K groups of input data in correspondence with an interleaving unit at a transmitter; an address generator for reading data written in the memory and generating memory addresses for writing input data; read-enable unit and write-enable unit for reading and writing data written at the generated memory addresses; and a controller for controlling the address generator to generate the memory addresses for the input data in correspondence with the deinterleaving units, the controller controlling the read-enable unit and the write-enable unit to read data written at the memory addresses before writing the input data at the memory addresses.
摘要翻译：公开了一种具有小型解交织器存储器的数字广播接收机的解交织设备和方法。解交织装置包括：具有存储空间的存储器，用于在与发送器处的交织单元对应的K组输入数据上执行多个解交织单元中的去交织; 用于读取写入存储器中的数据并产生用于写入输入数据的存储器地址的地址发生器; 读取使能单元和写入使能单元，用于读取和写入在所生成的存储器地址上写入的数据; 以及控制器，用于控制地址发生器以与解交错单元相对应地生成用于输入数据的存储器地址，控制器控制读取使能单元和写入使能单元在写入输入之前读取写入存储器地址的数据数据在存储器地址。

93. 发明授权

US06748033B1 De-interleave circuit 有权
标题翻译：去交错电路
公开(公告)号：US06748033B1
公开(公告)日：2004-06-08
申请号：US09743718
申请日：2001-01-16
申请人： Kenichi Shiraishi , Soichi Shinjo , Akihiro Horii
发明人： Kenichi Shiraishi , Soichi Shinjo , Akihiro Horii
IPC分类号： H04L2706
CPC分类号： H03M13/276 , H03M13/2735 , H03M13/2785
摘要： To provide a de-interleave circuit used for a BS digital broadcasting receiver. The de-interleave circuit is provided with less memory. An address data generator (3) supplies address data (A) to a de-interleave memory (4) in a de-interleave order. Each main signal is read from an address location in the de-interleave memory (4) specified by address data (A), and a following main signal is interleaved and written in that address location of the memory. As a result, the de-interleave memory (4) only requires space for one superframe.
摘要翻译：提供用于BS数字广播接收机的解交织电路。解交织电路具有较少的存储器。地址数据生成器（3）以去交织顺序将地址数据（A）提供给解交织存储器（4）。从由地址数据（A）指定的解交织存储器（4）中的地址位置读取每个主信号，并且将以下主信号交织并写入存储器的该地址位置。结果，解交织存储器（4）仅需要一个超帧的空间。

94. 发明申请

US20030226096A1 True bit level decoding of TTCM (Turbo Trellis Code Modulation ) 有权
标题翻译： TTCM的真位解码（Turbo Trellis Code Modulation）
公开(公告)号：US20030226096A1
公开(公告)日：2003-12-04
申请号：US10429362
申请日：2003-05-01
发明人： Ba-Zhong Shen , Kelly Brian Cameron , Hau Thien Tran
IPC分类号： H03M013/03
CPC分类号： H04L1/005 , H03M13/256 , H03M13/258 , H03M13/27 , H03M13/2767 , H03M13/2771 , H03M13/2785 , H03M13/2957 , H03M13/4123 , H03M13/4161 , H04L1/0055 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.
摘要翻译： TTCM（Turbo Trellis编码调制）的可变速率和信号星座的真位解码。提出了一种解码方法，其允许基于比特级的解码，其允许区分符号的各个比特。而现有技术方法通常在符号级基础上执行解码，这种解码方法允许改进的方法，其中可以针对信息符号的各个比特分别进行硬判决/最佳估计。此外，解码方法允许减少需要执行的计算的总数以及在迭代解码期间需要存储的值的总数。比特级解码方法还能够解码其码率和/或信号星座类型（和映射）可以在逐个符号的基础上变化的信号。

95. 发明申请

US20030226095A1 Efficient design to calculate extrinsic information for soft-in-soft-out (SISO) decoder 有权
标题翻译：高效的设计来计算软入软件（SISO）解码器的外在信息
公开(公告)号：US20030226095A1
公开(公告)日：2003-12-04
申请号：US10264766
申请日：2002-10-04
发明人： Kelly Brian Cameron , Hau Thien Tran
IPC分类号： H03M013/03
CPC分类号： H04L1/005 , H03M13/256 , H03M13/258 , H03M13/27 , H03M13/2767 , H03M13/2771 , H03M13/2785 , H03M13/2957 , H03M13/4123 , H03M13/4161 , H04L1/006 , H04L1/0066 , H04L1/0068 , H04L1/0071
摘要： Efficient design to calculate extrinsic information for Soft-In-Soft-Out (SISO) decoder. A design provides for very efficient performing extrinsic value calculation when performing iterative decoding. The design also accommodates a variety of rate controls each having varying bandwidth efficiencies. By grouping and capitalizing on the commonality of many of the intermediate terms that are employed when calculating the extrinsic values needed to perform iterative decoding, a great saving in terms of hardware may be achieved. In addition, this also provides a great deal of improvement in terms of operational speed and overall decoder system efficiency. The design is also adaptable to assist in performing decoding input symbols having multiple bits; a single design may be employed to accommodate different input symbols that have different numbers of bits. The extrinsic calculation employs min* processing in one embodiment; however, the design may also be performed using max*, min, or max processing.
摘要翻译：高效的设计来计算Soft-In-Soft-Out（SISO）解码器的外在信息。当进行迭代解码时，设计提供非常有效的执行外在值计算。该设计还适应各种具有不同带宽效率的速率控制。通过分组和利用在计算执行迭代解码所需的外在值时所采用的许多中间项的共同性，可以实现硬件方面的巨大的保存。此外，这也在操作速度和整体解码器系统效率方面提供了大量的改进。该设计还适于协助执行具有多个位的解码输入符号; 可以采用单一设计来适应具有不同位数的不同输入符号。在一个实施例中，外在计算采用最小值*处理; 然而，也可以使用max *，min或max处理来执行设计。

96. 发明申请

US20030115531A1 Turbo decoding apparatus and interleave-deinterleave apparatus 失效
公开(公告)号：US20030115531A1
公开(公告)日：2003-06-19
申请号：US10352515
申请日：2003-01-28
发明人： Kazuhisa Obuchi , Tetsuya Yano , Kazuo Kawabata , Takaharu Nakamura
IPC分类号： H03M013/00
CPC分类号： H03M13/2984 , H03M13/2707 , H03M13/275 , H03M13/2764 , H03M13/2767 , H03M13/2771 , H03M13/2782 , H03M13/2785 , H03M13/6505 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.

97. 发明授权

US06553517B1 Interleavers and de-interleavers 有权
公开(公告)号：US06553517B1
公开(公告)日：2003-04-22
申请号：US09545077
申请日：2000-04-07
申请人： Mohit K. Prasad
发明人： Mohit K. Prasad
IPC分类号： G11C2900
CPC分类号： H03M13/2785 , H03M13/2764
摘要： A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.

98. 发明授权

US5828671A Method and apparatus for deinterleaving an interleaved data stream 失效
标题翻译：用于对交错数据流进行解交织的方法和装置
公开(公告)号：US5828671A
公开(公告)日：1998-10-27
申请号：US633848
申请日：1996-04-10
申请人： Oscar Gustavo Vela , Kin Chau-Lee , Paul H. Kelley
发明人： Oscar Gustavo Vela , Kin Chau-Lee , Paul H. Kelley
IPC分类号： G06F11/00 , H03M13/27
CPC分类号： H03M13/2785
摘要： A method and apparatus deinterleave data blocks each transmitted as a sequence of data groups including N bits of data from a single bit position of N words. A first data block is received (1004) and stored (1006) in a memory (402) in a manner that defines memory locations for each of the N words, thereby deinterleaving the first data block. A next data block is received by processing (1008) at least a portion of the N words stored previously in the memory, thereby providing free memory locations, and thereafter receiving (1012) new data including at least a portion of a next data group of the next data block. The new data is stored (1014) in at least a portion of the free memory locations, and processing continues until the next data block has been received and stored in entirety. The memory locations are then redefined (1018) for the N words, thereby deinterleaving the next data block.
摘要翻译：一种方法和装置对作为包括来自N个字的单个位位置的N位数据的数据组序列发送的数据块进行解交织。接收第一数据块（1004）并以定义N个字中的每一个的存储器位置的方式存储（1006）到存储器（402）中，从而对第一数据块进行解交织。通过处理（1008）先前存储在存储器中的N个字的至少一部分来接收下一数据块，从而提供空闲存储器位置，然后接收（1012）新数据，包括下一数据组的至少一部分下一个数据块。新数据被存储在空闲存储器位置的至少一部分中（1014），并且处理继续，直到下一个数据块被完整地接收和存储。然后对N个字重新定义存储器位置（1018），从而对下一个数据块进行解交织。

99. 发明授权

US5056105A Interleaving method for a digital transmission system 失效
标题翻译：数字传输系统的交互方法
公开(公告)号：US5056105A
公开(公告)日：1991-10-08
申请号：US438380
申请日：1989-11-20
申请人： Marc Darmon , Philippe Sadot , Sami Harari
发明人： Marc Darmon , Philippe Sadot , Sami Harari
IPC分类号： H03M13/27
CPC分类号： H03M13/2785 , H03M13/2746
摘要： A psuedo-random interleaving method suitable for use in transmitting digital data. A pseudo-random pilot sequence is used for simultaneously reading from and writing to a vector of size Tv.gtoreq.Tc.times.Lm, the pilot sequence satisfying a minimum distance law Lm, except when blocking occurs. Deinterleaving is performed symmetrically by means of an inverse pilot sequence suitable for reconstituting successive code words.
摘要翻译：适用于传输数字数据的伪随机交错方法。伪随机导频序列用于同时读取和写入大小为Tv> / = TcxLm的矢量，导频序列满足最小距离定律Lm，除非发生阻塞。通过适用于重构连续码字的逆导频序列对称地执行去交织。

100. 发明授权

US4802170A Error disbursing format for digital information and method for organizing same 失效
标题翻译：数字信息的错误发放格式和组织方法
公开(公告)号：US4802170A
公开(公告)日：1989-01-31
申请号：US43939
申请日：1987-04-29
申请人： Lorne Trottier
发明人： Lorne Trottier
IPC分类号： G06F11/10 , G06F12/16 , G11B20/18 , H03M13/27
CPC分类号： H03M13/2785 , G11B20/1866 , H03M13/2707
摘要： Multiple stage interleaving through a memory matrix is utilized to separate adjacently disposed bits from bytes of digital information, in a reorganized bit stream. At least two stages of interleaving are required for the preferred embodiments of the invention which achieves a bit separation distance equal to the bit capacity of a plurality of either the matrix columns or rows, with that plurality being the number of adjacently disposed bits in each byte of digital information.
摘要翻译：利用存储器矩阵进行的多级交织用于在重组的比特流中将邻近位置的位与数字信息的字节分离。对于实现等于多个矩阵列或行的位容量的位分离距离的本发明的优选实施例，需要至少两个级别的交织，其中多个是每个字节中相邻布置的位的数量的数字信息。

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