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91. 发明授权

US09274892B2 Memory chip with error detection and retry modes of operation 有权
标题翻译：具有错误检测和重试操作模式的内存芯片
公开(公告)号：US09274892B2
公开(公告)日：2016-03-01
申请号：US14828013
申请日：2015-08-17
申请人： Rambus Inc.
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： G06F11/00 , G06F3/06 , G11C29/52 , G06F11/14 , G06F11/10 , G06F11/07 , H04L1/00 , H04L1/08 , H04L1/18
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

92. 发明申请

US20160041875A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
公开(公告)号：US20160041875A1
公开(公告)日：2016-02-11
申请号：US14920510
申请日：2015-10-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Shinichi KANNO , Hironori Uchikawa
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： H03M13/2906 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G06F13/1673 , G06F13/4068 , G11C29/52 , H03M13/03 , H03M13/29 , H03M13/35 , H03M13/6561 , Y02D10/14 , Y02D10/151
摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

93. 发明申请

US20150378817A1 Memory System With Error Detection And Retry Modes Of Operation 有权
标题翻译：具有错误检测和重试操作模式的存储系统
公开(公告)号：US20150378817A1
公开(公告)日：2015-12-31
申请号：US14827978
申请日：2015-08-17
申请人： Rambus Inc.
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

94. 发明申请

US20150349920A1 METHODS TO TRANSPORT FORWARD ERROR CORRECTION CODES IN A SYMBOL ENCODED TRANSMISSION STREAM 审中-公开
标题翻译：在符号编码传输流中传输前向纠错码的方法
公开(公告)号：US20150349920A1
公开(公告)日：2015-12-03
申请号：US14723075
申请日：2015-05-27
申请人： SAMSUNG DISPLAY CO., LTD
发明人： Dale F. Stolitzka , Jalil Kamali
IPC分类号： H04L1/00 , G06F11/10
CPC分类号： H04L1/0041 , G06F3/0619 , H03M13/03 , H03M13/1515 , H03M13/19 , H03M13/2906 , H03M13/2942 , H03M13/31 , H04L1/0043 , H04L1/0052 , H04L1/0057 , H04L1/0061 , H04L1/0065 , H04L1/0072 , H04L25/49
摘要： A method to transport forward error correction (FEC) codes in a symbol encoded transmission stream includes encoding a data stream from a data source into data symbols using computing circuits, generating first FEC codes from the data symbols using the computing circuits, encoding the first FEC codes into first FEC symbols using the computing circuits, merging the data symbols and the first FEC symbols into the transmission stream using the computing circuits, and transmitting the merged transmission stream to a sink device using the computing circuits. The encoding of the data stream into the data symbols and the encoding of the first FEC codes into the first FEC symbols may include the same encoding technique.
摘要翻译：在符号编码的传输流中传输前向纠错（FEC）码的方法包括使用计算电路将数据流中的数据流编码成数据符号，使用计算电路从数据符号生成第一个FEC码，对第一个FEC进行编码使用计算电路将第一FEC符号编码成第一FEC符号，使用计算电路将数据符号和第一FEC符号合并到传输流中，以及使用计算电路将合并的传输流发送到宿设备。将数据流编码到数据符号中并将第一FEC码编码到第一FEC符号中可以包括相同的编码技术。

95. 发明授权

US09059735B2 Decoding method and decoding device 有权
标题翻译：解码方式和解码装置
公开(公告)号：US09059735B2
公开(公告)日：2015-06-16
申请号：US13873765
申请日：2013-04-30
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Yang Li , Lili Jin , Yu Zhao , Zhiyu Xiao
IPC分类号： H03M13/00 , H03M13/03 , H03M13/27 , H03M13/29 , H03M13/15
CPC分类号： H03M13/03 , H03M13/1515 , H03M13/152 , H03M13/2732 , H03M13/2918 , H03M13/2927
摘要： Embodiments of the present invention provide a decoding method and a decoding device. The method includes: performing iterative decoding on a multidimensional code to obtain incorrigible code words; determining locations of error bits in the incorrigible code words that are obtained by performing the iterative decoding on the multidimensional code, where the locations of error bits in the incorrigible code words are multidimensional coordinate locations of the error bits in the multidimensional code; correcting error bits of a part of the incorrigible code words in the multidimensional code according to the determined locations of the error bits in the incorrigible code words; and after the error bits of a part of the incorrigible code words in the multidimensional code are corrected, performing iterative decoding on the multidimensional code The embodiments of the present invention are applicable to the field of decoding technologies.
摘要翻译：本发明的实施例提供一种解码方法和解码装置。该方法包括：对多维码执行迭代解码以获得不可兑换的码字; 确定通过对多维码执行迭代解码获得的不可兑换码字中的错误位的位置，其中不可兑换码字中的错误位的位置是多维码中的错误位的多维坐标位置; 根据确定的不可兑换代码字中的错误位的位置，校正多维代码中不可兑换代码字的一部分的错误位; 并且在多维码中的不可兑换代码字的一部分的错误位被校正之后，对多维代码执行迭代解码。本发明的实施例可应用于解码技术领域。

96. 发明申请

US20150067447A1 METHOD, APPARATUS AND DEVICE FOR DATA PROCESSING 有权
标题翻译：用于数据处理的方法，装置和装置
公开(公告)号：US20150067447A1
公开(公告)日：2015-03-05
申请号：US14018811
申请日：2013-09-05
申请人： Infineon Technologies AG
发明人： Jan Otterstedt , Rainer Goettfert
IPC分类号： G06F11/10
CPC分类号： H04L1/0057 , G06F11/1012 , G06F11/1024 , G06F11/1048 , G06F11/1068 , H03M13/03 , H03M13/098 , H03M13/1174 , H03M13/19 , H03M13/2906
摘要： An embodiment relates to a method for data processing that includes reading data, the data comprising overhead information and payload information, and determining a state of each portion of the data, wherein the state is one of a first binary state, a second binary state, and an undefined state. The method also includes decoding at least one portion of data that has an undefined state based on its location and based on the overhead information.
摘要翻译：一个实施例涉及一种用于数据处理的方法，包括读取数据，包括开销信息和有效载荷信息的数据，以及确定数据的每个部分的状态，其中状态是第一二进制状态，第二二进制状态，和一个未定义的状态。该方法还包括基于其位置并基于开销信息来解码具有未定义状态的数据的至少一部分。

97. 发明授权

US08964831B2 Apparatus and method for encoding and decoding signals 有权
标题翻译：用于对信号进行编码和解码的装置和方法
公开(公告)号：US08964831B2
公开(公告)日：2015-02-24
申请号：US12599391
申请日：2008-05-16
申请人： Richard W. Citta , Scott M. LoPresto
发明人： Richard W. Citta , Scott M. LoPresto
IPC分类号： H04N7/12 , H04N19/61 , H04N19/172 , H04N19/176 , H03M13/00 , H03M13/03 , H03M13/09
CPC分类号： H04N7/50 , H03M13/00 , H03M13/03 , H03M13/09 , H03M13/095 , H03M13/096 , H03M13/134 , H03M13/151 , H03M13/253 , H03M13/2906 , H03M13/41 , H03M13/6356 , H03M13/6362 , H03M13/6538 , H04L1/005 , H04L1/0065 , H04L1/0072 , H04L1/0079 , H04N7/52 , H04N19/156 , H04N19/157 , H04N19/172 , H04N19/176 , H04N19/61
摘要： New capabilities will allow conventional broadcast transmission to be available to mobile devices. A method is described including receiving a data set, extracting a subset, encoding the subset using a first encoding process, combining the encoded subset with the remaining portion, and encoding the combined data set including the appended subset using a second encoding process. an apparatus is described including means for extracting a subset, means for first encoding, means for combining, and means for second encoding. An apparatus for decoding includes a data identifier receiving a data set and identifying a subset of data, a first decoder decoding the subset using a first decoding process, and a second decoder combining the subset of data with a remaining portion of the data set and decoding the combined data using a second decoding process. A method for decoding is also described.
摘要翻译：新功能将允许传统的广播传输可用于移动设备。描述了一种方法，包括接收数据集，提取子集，使用第一编码过程编码子集，将编码的子集与剩余部分组合，以及使用第二编码过程对包括附加子集的组合数据集进行编码。描述了一种装置，其包括用于提取子集的装置，用于第一编码的装置，用于组合的装置和用于第二编码的装置。一种用于解码的装置包括接收数据集并识别数据子集的数据标识符，使用第一解码处理解码子集的第一解码器，以及将数据子集与数据集的剩余部分组合的解码器使用第二解码处理的组合数据。还描述了一种用于解码的方法。

98. 发明授权

US08935527B2 Secure transmission with error correcting code 有权
标题翻译：安全传输带纠错码
公开(公告)号：US08935527B2
公开(公告)日：2015-01-13
申请号：US12086899
申请日：2006-12-20
申请人： Aurelien Francillon , Vincent Roca , Christoph Neumann , Pascal Moniot
发明人： Aurelien Francillon , Vincent Roca , Christoph Neumann , Pascal Moniot
IPC分类号： H04L9/32 , H03M13/03 , H03M13/00 , H04L1/00 , H04L9/06 , H04L9/08 , H03M13/11 , H03M13/37
CPC分类号： H03M13/03 , H03M13/033 , H03M13/1102 , H03M13/3761 , H03M13/63 , H04L1/0041 , H04L1/0057 , H04L9/06 , H04L9/08 , H04L2209/34
摘要： The invention concerns a method and a system for encoding digital data (DATA) represented by source symbols, with an error correcting code generating parity symbols from, for each parity symbol, a plurality of source symbols and at least one parity symbol of preceding rank, including at least encrypting once (54) at least one first value (P1) into several encrypted values and integrating at least one combination (P1,j) of said encrypted values to compute (55) at least one part (P2 . . . Pn−k) of said parity symbols.
摘要翻译：本发明涉及一种用于对由源符号表示的数字数据（DATA）进行编码的方法和系统，其中纠错码从每个奇偶校验符号产生奇偶校验符号，多个源符号和至少一个先前秩的奇偶校验符号，包括至少将至少一个第一值（54）加密（54）至几个加密值并且对所述加密值的至少一个组合（P1，j）进行加密，以计算（55）至少一个部分（P2 ... Pn -k）所述奇偶校验符号。

99. 发明申请

US20140380118A1 UNEQUAL ERROR PROTECTION SCHEME FOR HEADERIZED SUB DATA SETS 有权
标题翻译：用于高级子数据集的不平等错误保护方案
公开(公告)号：US20140380118A1
公开(公告)日：2014-12-25
申请号：US14477647
申请日：2014-09-04
申请人： International Business Machines Corporation
发明人： Roy D. Cideciyan , Robert A. Hutchins , Thomas Mittelholzer , Keisuke Tanaka
IPC分类号： G06F11/10
CPC分类号： G06F11/1012 , G11B7/007 , G11B20/1809 , G11B20/1833 , G11B20/1866 , G11B2020/1836 , H03M13/03 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/2909 , H03M13/2924 , H03M13/293 , H03M13/356 , H03M13/373 , H03M13/3746 , H04L1/0061
摘要： A method for decoding a headerized sub data set (SDS) according to one embodiment includes decoding a header from a headerized SDS to obtain a SDS. C1 and C2 decoding are performed on the SDS in a number of iterations based on a number of interleaves in each row of the SDS. A number of columns of the SDS are overwritten with successfully decoded C2 codewords. A number of rows of the SDS are overwritten with successfully decoded C1 codewords. A number of C1 and/or C2 codewords of the SDS are erased. Remaining rows and/or columns of the SDS are maintained as uncorrected. The SDS is output when all rows of the SDS include only C1 codewords and all columns of the SDS include only C2 codewords.
摘要翻译：根据一个实施例的用于对标题化子数据集（SDS）进行解码的方法包括从标题化的SDS解码报头以获得SDS。基于SDS的每行中的交织数量，在SDS上执行C1和C2解码。 SDS的许多列被成功解码的C2码字覆盖。 SDS的许多行被成功解码的C1码字覆盖。 SDS的多个C1和/或C2码字被擦除。 SDS的剩余行和/或列保持为未校正。当SDS的所有行仅包含C1码字时，输出SDS，SDS的所有列仅包括C2码字。

100. 发明授权

US08918703B2 Memory system with error detection and retry modes of operation 有权
标题翻译：具有错误检测和重试操作模式的内存系统
公开(公告)号：US08918703B2
公开(公告)日：2014-12-23
申请号：US13730942
申请日：2012-12-29
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： G11C29/00 , H03M13/00 , G06F11/10 , G06F11/14 , H04L1/00 , H04L1/08 , H04L1/18 , G06F11/00
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

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