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91. 发明申请

US20140210532A1 Phase-Locked Loop Apparatus and Method 审中-公开
标题翻译：锁相环设备及方法
公开(公告)号：US20140210532A1
公开(公告)日：2014-07-31
申请号：US14167852
申请日：2014-01-29
申请人： Julian Jenkins
发明人： Julian Jenkins
IPC分类号： H03L7/197
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/16 , H03L2207/50
摘要： A PLL includes an oscillator, a time-to-digital converter (TDC) and a system for the remaining functionality. The TDC measures the oscillator's phase against a reference clock. The measured phase has an integer part obtained from a modulus-K counter, and a fractional part measured by a fine TDC. The system compares the measured phase with a desired phase, and filters it to obtain a parameter that controls the oscillator frequency. The TDC may also include a synchronization block to align the fine TDC and a pulse hider to reduce the power used by the fine TDC. The system may include an integrator to calculate the integer part of the desired phase, a second integrator to calculate the fractional part, and an interpolator for an even finer fraction. A method to obtain fast lock includes using the phase error rate of change to control the oscillator frequency.
摘要翻译： PLL包括振荡器，时间 - 数字转换器（TDC）和用于剩余功能的系统。 TDC根据参考时钟测量振荡器的相位。测量相位具有从模数K计数器获得的整数部分和通过精细TDC测量的分数部分。该系统将测量的相位与期望的相位进行比较，并对其进行滤波以获得控制振荡器频率的参数。 TDC还可以包括同步块以对准精细TDC和脉冲隐藏器以减少由精细TDC使用的功率。该系统可以包括用于计算期望相位的整数部分的积分器，用于计算分数部分的第二积分器，以及用于更精细分数的内插器。获得快速锁定的方法包括使用相位误差率来控制振荡器频率。

92. 发明授权

US08780974B2 Digital PLL circuit and communication device 有权
标题翻译：数字PLL电路和通信设备
公开(公告)号：US08780974B2
公开(公告)日：2014-07-15
申请号：US13049645
申请日：2011-03-16
申请人： Fumiaki Senoue , Kouji Okamoto
发明人： Fumiaki Senoue , Kouji Okamoto
IPC分类号： H04N7/12 , H03L7/091 , H03L7/087
CPC分类号： H03L7/087 , H03L7/091 , H03L2207/50
摘要： In a digital PLL circuit outputting a clock signal with a frequency obtained by multiplying a frequency of a reference signal by a frequency command word (a frequency ratio), an RPA serially adds a frequency command word containing a fractional component. An output of the RPA is input to a minute phase error generator. The phase error generator generates a plurality of threshold values close to an actual amplitude value of the reference signal based on the fractional portion of the serially added value of the frequency command word, calculates the amplitude value of the reference signal and a phase error of the reference signal corresponding to the amplitude value based on the threshold values, and calculates a minute phase error between the reference signal and the output clock.
摘要翻译：在通过将参考信号的频率乘以频率指令字（频率比）而获得的频率输出时钟信号的数字PLL电路中，RPA串行地添加包含分数分量的频率指令字。 RPA的输出被输入到微小的相位误差发生器。相位误差发生器基于频率指令字的串行相加值的小数部分产生接近参考信号的实际振幅值的多个阈值，计算参考信号的振幅值和相位误差的相位误差基于阈值对应于振幅值的参考信号，并计算参考信号和输出时钟之间的微小相位误差。

93. 发明授权

US08723607B2 Phase locked loop 有权
标题翻译：锁相环
公开(公告)号：US08723607B2
公开(公告)日：2014-05-13
申请号：US12678106
申请日：2008-08-19
申请人： Michael Story , Nicolas Sornin
发明人： Michael Story , Nicolas Sornin
IPC分类号： H03L7/099 , H03J7/04 , H03L7/02
CPC分类号： H03L7/085 , H03C5/00 , H03L7/091 , H03L2207/50 , H04L27/361
摘要： A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input to the oscillator; sampling means for generating a sequence of digital values representing the output of the oscillator at moments synchronized with a reference frequency; a difference unit for generating a feedback signal representing the difference between successive values in the sequence; and an integrator for integrating the difference between the feedback signal and a signal of a desired output frequency; the signal input to the oscillator being dependent on the output of the integrator.
摘要翻译：一种锁相环，包括：振荡器，用于产生取决于对所述振荡器的输入的频率的输出信号; 采样装置，用于在与参考频率同步的时刻产生表示振荡器的输出的数字值序列; 差分单元，用于产生表示序列中连续值之差的反馈信号; 以及积分器，用于对反馈信号与期望输出频率的信号之间的差进行积分; 输入到振荡器的信号取决于积分器的输出。

94. 发明授权

US08710884B2 Methods and devices for multiple-mode radio frequency synthesizers 有权
标题翻译：多模射频合成器的方法和装置
公开(公告)号：US08710884B2
公开(公告)日：2014-04-29
申请号：US13406246
申请日：2012-02-27
申请人： Olivier Burg , Cao-Thong Tu
发明人： Olivier Burg , Cao-Thong Tu
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.
摘要翻译：方法和装置提供用于基于参考频率信号来确定是否在第一操作模式或第二操作模式中操作射频合成器。射频合成器包括配置成产生具有输出频率的振荡器信号的数字控制振荡器。数字频率锁定环被配置为基于第一控制信号来控制处于第一操作模式的振荡器信号的输出频率。数字锁相环被配置为基于第二控制信号在第二操作模式中控制振荡器信号的输出频率。控制器基于参考频率信号来确定是否在第一模式或第二模式中操作。控制器基于分别在第一或第二模式中的操作的确定来产生第一或第二控制信号。

95. 发明申请

US20140084978A1 Digitally Controlled Oscillator with Thermometer Sigma Delta Encoded Frequency Control Word 有权
标题翻译：数字控制振荡器与温度计Sigma Delta编码频率控制字
公开(公告)号：US20140084978A1
公开(公告)日：2014-03-27
申请号：US14028449
申请日：2013-09-16
申请人： Entropic Communications, Inc.
发明人： Josephus A. van Engelen , Hairong Yu , Howard A. Baumer
IPC分类号： H03L7/099
CPC分类号： H03L7/0991 , H03L1/022 , H03L7/099 , H03L7/104 , H03L7/1075 , H03L7/183 , H03L2207/06 , H03L2207/50
摘要： Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.
摘要翻译：公开了用于产生用于控制根据本发明的实施例的数字控制振荡器的温度计Σ-Δ编码频率控制字的系统和方法。在一个实施例中，用于产生输出时钟信号的全数字锁相环包括：温度计脉冲编码器，被配置为产生包括温度计编码信号和脉冲调制抖动信号的频率控制字（FCW），并且发送脉冲调制抖动信号通过选定的FCW信号线传送温度计编码信号，并通过其它FCW信号线传送温度计编码信号，以及数字控制振荡器，以接收包含组合温度计和脉冲调制信号的FCW，并产生输出时钟信号。

96. 发明申请

US20140035684A1 CONTROL CIRCUIT AND APPARATUS FOR DIGITALLY CONTROLLED OSCILLATOR 审中-公开
标题翻译：数字控制振荡器的控制电路和设备
公开(公告)号：US20140035684A1
公开(公告)日：2014-02-06
申请号：US13675630
申请日：2012-11-13
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD. , RESEARCH & BUSINESS FOUNDATION SUNGK
发明人： Yoo Sam NA , Kang Yoon LEE , Dong Su LEE , Hyung Gu PARK , Hong Jin KIM , Gyu Suck KIM , Young Gun PU
IPC分类号： H03L5/00 , H03L7/06
CPC分类号： H03L5/00 , H03L7/06 , H03L7/08 , H03L2207/50
摘要： There are provided a control circuit for a digitally controlled oscillator and a control apparatus for a digitally controlled oscillator using the same. The control circuit for a digitally controlled oscillator includes: a peak detection circuit detecting amplitude of a signal output from the digitally controlled oscillator; and a transconductance control circuit comparing an output of the peak detection circuit with a predetermined reference signal to control a transconductance value of a negative transconductance circuit included in the digitally controlled oscillator.
摘要翻译：提供了一种用于数字控制振荡器的控制电路和使用该控制振荡器的数控振荡器的控制装置。用于数字控制振荡器的控制电路包括：峰值检测电路，检测从数字控制振荡器输出的信号的振幅; 以及跨导控制电路，将峰值检测电路的输出与预定参考信号进行比较，以控制数字控制振荡器中包括的负跨导电路的跨导值。

97. 发明授权

US08638147B2 Clock generator and system including the same 有权
标题翻译：时钟发生器和系统包括相同的
公开(公告)号：US08638147B2
公开(公告)日：2014-01-28
申请号：US13964584
申请日：2013-08-12
申请人： Fujitsu Limited
发明人： Atsushi Matsuda
IPC分类号： H03L7/06
CPC分类号： H03L7/148 , H03L7/107 , H03L7/16 , H03L2207/50
摘要： A clock generator includes a digitally controlled oscillator configured to generate an output clock having a frequency depending on an input code; a phase comparison section configured to output a phase difference signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; a low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.
摘要翻译：时钟发生器包括被配置为产生具有取决于输入代码的频率的输出时钟的数字控制振荡器; 相位比较部，被配置为通过将参考相位与输出时钟的相位进行比较来输出相位差信号，所述参考相位基于输入时钟和预定的倍频数; 低通滤波器，被配置为通过对相位差信号进行滤波来提供数字控制振荡器的输入码; 波形发生部分，被配置为产生预定的扩频波，所述预定的扩频波将被加上倍频号和输入码; 以及检测/补偿部，被配置为补偿输入代码，使得相位差减小，从相位差信号检测相位差。

98. 发明授权

US08604851B2 Digital phase locked loop device and method in wireless communication system 有权
标题翻译：无线通信系统中的数字锁相环装置及方法
公开(公告)号：US08604851B2
公开(公告)日：2013-12-10
申请号：US13817816
申请日：2011-08-19
申请人： Kang-Yoon Lee , Young-Gun Pu , An-Soo Park , Joon-Sung Park , Jae-Sup Lee
发明人： Kang-Yoon Lee , Young-Gun Pu , An-Soo Park , Joon-Sung Park , Jae-Sup Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/085 , H03L7/18 , H03L2207/50
摘要： A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.
摘要翻译：提供了无线通信系统中的数字锁相环（PLL）。 PLL包括数字控制振荡器（DCO），分频器，相位频率检测器（PFD），时间到数字转换器（TDC），延迟比较器和电平定标器。 DCO根据输入数字调谐字（DTW）产生频率信号。分频器以整数比除成频率信号。 PFD产生表示分频信号和参考信号之间的相位差的信号。 TDC使用表示相位差的信号来测量相位差的时间间隔。延迟比较器计算上升沿与TDC测量值相符的时间间隔。级别缩放器生成使用表示时间间隔的数字代码来操作DCO的DTW。

99. 发明授权

US08565361B2 Synchronization distribution in microwave backhaul networks 有权
公开(公告)号：US08565361B2
公开(公告)日：2013-10-22
申请号：US12861786
申请日：2010-08-23
申请人： Philip Secker , Peter Croy
发明人： Philip Secker , Peter Croy
IPC分类号： H04L7/00
CPC分类号： H04W56/0015 , H03L7/08 , H03L7/18 , H03L2207/50 , H04J3/0602 , H04J3/0617 , H04J3/0638 , H04J3/0641 , H04J3/0647 , H04J3/065 , H04J3/0658 , H04J3/0679 , H04J3/0688
摘要： In some embodiments, a system comprises a clock, a root node, a radio channel network, and first and second child nodes. The clock may be configured to generate a clock signal. The root node may be configured to generate a first frame including a first payload and a first overhead and generate a second frame including a second payload and a second overhead. The first and second overheads may comprise a synchronization value based on the clock signal. The radio channel network may be in communication with the root node for transmitting the first and second frames. Each first and second child nodes may be configured to perform clock recovery including frequency synchronization using the synchronization value and a respective phase-lock loop.

100. 发明授权

US08537953B2 Time-interleaved clock-data recovery and method thereof 有权
标题翻译：时间交织时钟数据恢复及其方法
公开(公告)号：US08537953B2
公开(公告)日：2013-09-17
申请号：US12210190
申请日：2008-09-13
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03D3/24
CPC分类号： H04L7/033 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/0995 , H03L2207/50 , H03M1/745
摘要： A clock-data recovery (CDR) that employs a time-interleaved scheme is disclosed. The circuit comprises: a time-interleaved sampler/phase-detector circuit for receiving an input voltage signal and a plurality of clock signals and outputting N-bit data and N phase signals, wherein N is an integer greater than 1; a control circuit, coupled to the time-interleaved sampler/phase-detector circuit, for receiving the N phase signals and converting the N phase signals into a control signal; and a controlled oscillator, coupled to the control circuit, for generating the plurality of clock signals under the control of the control signal. The CDR is used to relax circuit speed requirement by time-interleaving phase detection by using a multi-phase lower speed circuit.
摘要翻译：公开了采用时间交织方案的时钟数据恢复（CDR）。该电路包括：时间交织采样器/相位检测器电路，用于接收输入电压信号和多个时钟信号并输出N位数据和N相信号，其中N是大于1的整数; 耦合到时间交织采样器/相位检测器电路的控制电路，用于接收N相信号并将N相信号转换成控制信号; 以及耦合到控制电路的受控振荡器，用于在控制信号的控制下产生多个时钟信号。 CDR用于通过使用多相低速电路的时间交织相位检测来放松电路速度要求。

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