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    • 93. 发明授权
    • Hybrid microelectronic array structure having electrically isolated supported islands, and its fabrication
    • 具有电隔离的支撑岛的混合微电子阵列结构及其制造
    • US06828545B1
    • 2004-12-07
    • US09859575
    • 2001-05-15
    • William J. Hamilton, Jr.Eli E. GordonRonald W. Berry
    • William J. Hamilton, Jr.Eli E. GordonRonald W. Berry
    • H01L3100
    • H01L27/1465H01L2924/351
    • A hybrid microelectronic array structure is fabricated from a readout integrated circuit array of microelectronic integrated circuits and a supported array of supported islands. The supported islands include one or more supported elements, with a respective supported element for each of the readout integrated circuits. The supported array is made by depositing the first semiconductor region onto a supported substrate and depositing the second semiconductor region onto the first semiconductor region, and defining supported islands as electrically isolated segments. On each supported element, a first interconnect is formed to the first semiconductor region and a second interconnect is formed to the second semiconductor region. The supported array is joined to the readout integrated circuit array by an interconnect structure, preferably a bump interconnect structure, to form the hybrid microelectronic array structure, with each readout integrated electrically interconnected to the respective one of the supported elements.
    • 混合微电子阵列结构由微电子集成电路的读出集成电路阵列和支持的岛的支持阵列制成。 支撑的岛包括一个或多个受支撑的元件,以及用于每个读出集成电路的相应的支撑元件。 支撑的阵列通过将第一半导体区域沉积到受支撑的衬底上并将第二半导体区域沉积到第一半导体区域上并且将支撑的岛作为电隔离段来制造。 在每个支撑元件上,第一互连形成于第一半导体区域,第二互连形成于第二半导体区域。 支撑的阵列通过互连结构(优选地是凸块互连结构)连接到读出集成电路阵列,以形成混合微电子阵列结构,其中每个读出器电互连到相应的一个支持元件。
    • 95. 发明申请
    • Monolithic infrared focal plane array detectors
    • 单片红外焦平面阵列检测器
    • US20030102432A1
    • 2003-06-05
    • US09833363
    • 2001-04-12
    • EPIR LTD.
    • Paul BoieriuRenganathan AshokanYuanping ChenJean-Pierre FaurieSivalingam Sivananthan
    • G01T001/24H01L027/14
    • H01L27/14687H01L27/14609H01L27/1465H01L27/14652H01L27/1469
    • An infrared sensing device including a multi-layer II-VI semiconductor material grown by molecular beam epitaxy on a readout circuit fabricated on silicon substrate having a orientation one degree tilted from the (100) direction is provided in this invention. A method to grow single crystalline mercury cadmium telluride multi-layer structure on custom-designed readout circuit (ROIC) is provided. Due to the height difference of more than 15 micron between the two planes containing the detector output gates and the ROIC signal input gates, a mesa with at least one sloped side is fabricated and the interconnecting metal electrodes running on them to connect the detector output to ROIC input. Planar photovoltaic junctions are fabricated selectively on the II-VI mesa structure formed on ROIC. At least one infrared detecting cell being formed in the mesa, with a conductor interconnect layer connecting the detection cell to the readout integrated circuit. Another design to simultaneously produce two linear arrays of monolithic infrared detectors is provided by the suitable design of the ROIC input pads and the infrared detector arrays.
    • 在本发明中提供了一种红外感测装置,其包括通过分子束外延生长的多层II-VI半导体材料,其制造在具有从(100)方向倾斜一度的硅衬底上的读出电路上。 提供了一种在定制设计的读出电路(ROIC)上生长单晶碲化镉多层结构的方法。 由于在包含检测器输出门和ROIC信号输入门的两个平面之间的高度差超过15微米,制造了具有至少一个倾斜侧的台面,并且互连金属电极在其上运行以将检测器输出连接到 ROIC输入。 选择性地在ROIC上形成的II-VI台面结构上制造平面光电结。 在台面中形成至少一个红外线检测单元,其中导体互连层将检测单元连接到读出集成电路。 通过ROIC输入焊盘和红外探测器阵列的合适设计,提供了同时生产两个线性阵列的单片红外探测器的另一种设计。
    • 99. 发明授权
    • Hybrid infrared ray detector with an improved bonding structure between
an Si-substrate having integrated circuits and an HgCdTe layer having
two-dimensional photodiode arrays and method for fabricating the same
    • 在具有集成电路的Si衬底和具有二维光电二极管阵列的HgCdTe层之间具有改进的结合结构的混合式红外线探测器及其制造方法
    • US5696377A
    • 1997-12-09
    • US631966
    • 1996-04-15
    • Masayuki Kanzaki
    • Masayuki Kanzaki
    • G01J1/02H01L21/60H01L21/603H01L27/14H01L27/146H01L31/02H01L31/10
    • H01L27/1465
    • A hybrid infrared ray detector includes a first semiconductor substrate which has a first thickness and a first elastic coefficient. A buffer layer is provided on the first semiconductor substrate which is made of a first compound semiconductor having a second elastic coefficient larger than the first elastic coefficient and which has a second thickness smaller than the first thickness. An epitaxial layer is provided on the buffer layer. The epitaxial layer is made of a second compound semiconductor having a third elastic coefficient smaller than the second elastic coefficient and larger than the first elastic coefficient and which has a third thickness which is almost the same as the second thickness. Two-dimensional arrays of photodiodes are provided on a surface of the epitaxial layer. First bumps are provided on the photodiodes. Second bumps are provided on the surface of the epitaxial layer. The second bumps are positioned outside the two-dimensional arrays of the photodiodes. A second semiconductor substrate is provided which has integrated circuits, and third bumps positioned to correspond to the first bumps and fourth bumps positioned to correspond to the second bumps. The second semiconductor substrate is bonded via the first to the fourth bumps to the epitaxial layer. The second semiconductor substrate has a fourth thickness which is almost the same as the first thickness, and a fourth elastic coefficient which is almost the same as the first elastic coefficient. The first to fourth thickness and the first to fourth elastic coefficients are determined that a thermal stress caused by cooling the hybrid infrared ray detector is concentrated within the buffer layer.
    • 混合红外线检测器包括具有第一厚度和第一弹性系数的第一半导体衬底。 缓冲层设置在第一半导体衬底上,该第一半导体衬底由具有大于第一弹性系数的第二弹性系数的第一化合物半导体制成,并具有小于第一厚度的第二厚度。 在缓冲层上设置外延层。 外延层由具有小于第二弹性系数的第三弹性系数并且大于第一弹性系数的第二化合物半导体制成,并且具有与第二厚度几乎相同的第三厚度。 光电二极管的二维阵列设置在外延层的表面上。 在光电二极管上提供第一凸点。 在外延层的表面上设置第二凸块。 第二凸起位于光电二极管的二维阵列之外。 提供了具有集成电路的第二半导体衬底,并且第三凸起被定位成对应于第一凸块和第四凸起,所述第四凸起被定位成对应于第二凸块。 第二半导体衬底经由第一至第四凸块接合到外延层。 第二半导体衬底具有与第一厚度几乎相同的第四厚度和与第一弹性系数几乎相同的第四弹性系数。 确定第一至第四厚度和第一至第四弹性系数,使得通过冷却混合红外线检测器引起的热应力集中在缓冲层内。
    • 100. 发明授权
    • Monolithic-hybrid radiation detector/readout
    • 单片混合放射线检测器/读数
    • US5670817A
    • 1997-09-23
    • US397818
    • 1995-03-03
    • David A. Robinson
    • David A. Robinson
    • H01L27/146H01L31/00
    • H01L27/1465
    • Methods are disclosed for fabricating a monolithic array of radiation detectors and associated readout circuits, as are monolithic arrays fabricated by the methods. One method includes the steps of (a) providing a first substrate (10) having a first major surface (10a) and an oppositely disposed second major surface (10b); (b) doping the first major surface with a dopant having a first type of electrical conductivity to form a first doped region (12) adjacent to the first major surface; (c) forming an electrically insulating dielectric layer (14) on the first major surface; (d) thermally bonding a second substrate to the dielectric layer and thinning the second substrate to provide a semiconductor layer (16) having a predetermined thickness; (e) delineating the semiconductor layer into a plurality of adjacently disposed electrically isolated regions each of which corresponds to a radiation detector unit cell; (f) fabricating a readout integrated circuit (17) within a portion of the semiconductor layer within each of the unit cells; (g) conductively coupling (22, 23) each of the readout integrated circuits to an underlying portion of the first doped region; and (h) doping the second major surface with a dopant having a second type of electrical conductivity to form a second doped region (24) adjacent to the second major surface. The second major surface is a radiation receiving surface of the monolithic array.
    • 公开了用于制造辐射检测器和相关联的读出电路的单片阵列的方法,以及通过该方法制造的单片阵列。 一种方法包括以下步骤:(a)提供具有第一主表面(10a)和相对设置的第二主表面(10b)的第一基底(10); (b)用具有第一类型导电性的掺杂剂掺杂第一主表面以形成与第一主表面相邻的第一掺杂区域(12); (c)在所述第一主表面上形成电绝缘介电层(14); (d)将第二衬底热粘合到电介质层并使第二衬底变薄以提供具有预定厚度的半导体层(16); (e)将半导体层描绘成多个相邻设置的电隔离区域,每个区域对应于辐射检测器单元; (f)在每个单元电池内的半导体层的一部分内制造读出集成电路(17); (g)将所述读出集成电路中的每一个导通地耦合(22,23)到所述第一掺杂区域的下部; 和(h)用具有第二类型导电性的掺杂剂掺杂第二主表面以形成与第二主表面相邻的第二掺杂区域(24)。 第二主表面是整体阵列的辐射接收表面。