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91. 发明申请

US20020094676A1 Salicide integrated solution for embedded virtual-ground memory 有权
标题翻译：用于嵌入式虚拟地面存储器的杀虫剂集成解决方案
公开(公告)号：US20020094676A1
公开(公告)日：2002-07-18
申请号：US09760597
申请日：2001-01-16
发明人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang
IPC分类号： H01L021/44
CPC分类号： H01L27/112 , H01L21/743 , H01L27/105 , H01L27/11286
摘要： A salicide integrate solution for embedded virtual-ground memory of the present invention provides a controlled distance between poly gates. In this way, the spacers formed on the sidewalls of the poly gates become self fill-upon spacers, and the surface of the substrate is not exposed. Thus, the salicides will not be formed on the surface of the substrate causing the connection of the buried diffusion regions. Moreover, the present invention provides two dummy poly gates located on the outside of the poly gates, so that the buried diffusion regions on the surface of the embedded virtual-ground memory are covered by the poly gates and self fill-up spacer. Utilizing the present invention, the process of forming salicides on the memory cell region and the peripheral logic region can be integrated together.
摘要翻译：本发明的用于嵌入式虚拟地面存储器的自对准一体化解决方案提供了多门之间的受控距离。以这种方式，形成在多晶硅栅极的侧壁上的间隔物成为自填充间隔物，并且基板的表面不暴露。因此，不会在衬底的表面上形成防止埋藏扩散区域的连接的杀螨剂。此外，本发明提供了位于多晶硅栅极外部的两个虚拟多晶硅栅极，使得嵌入式虚拟地存储器表面上的掩埋扩散区域被多晶硅栅极和自填充间隔物覆盖。利用本发明，可以将在存储单元区域和外围逻辑区域上形成杀生物剂的过程集成在一起。

92. 发明授权

US5403764A Method for producing a ROM on a semiconductor device having a nonvolatile memory 失效
标题翻译：在具有非易失性存储器的半导体器件上制造ROM的方法
公开(公告)号：US5403764A
公开(公告)日：1995-04-04
申请号：US37439
申请日：1993-03-26
申请人： Hiroki Yamamoto , Hiroshi Oji
发明人： Hiroki Yamamoto , Hiroshi Oji
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792 , A01L21/265
CPC分类号： H01L27/112 , H01L27/105 , H01L27/11286 , H01L27/11526
摘要： In a method for producing a semiconductor device having a nonvolatile memory capable of electrically writing, reading and erasing, and a read only memory; the improvement wherein the method includes a step of writing a state of "0" or "1" in the read only memory by doping said read only memory with an impurity for adjusting a threshold voltage of the read only memory, and steps for producing the read only memory other than the step of writing are the same as steps for producing the nonvolatile memory.
摘要翻译：一种具有能够进行电写入，读取和擦除的非易失性存储器的半导体器件的制造方法和只读存储器; 改进之处在于，该方法包括通过用用于调整只读存储器的阈值电压的杂质掺杂所述只读存储器将只读存储器中的“0”或“1”状态写入的步骤，以及用于产生只读存储器而不是写入步骤与产生非易失性存储器的步骤相同。

93. 发明申请

US20190157279A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190157279A1
公开(公告)日：2019-05-23
申请号：US16237913
申请日：2019-01-02
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Youngbeom PYON , Kichul PARK , Inkwon KIM , Ki Hoon JANG , Byoungho KWON , Sangkyun KIM , Boun YOON
IPC分类号： H01L27/112 , H01L23/535 , H01L23/528 , H01L27/11582 , H01L27/11575 , H01L27/11573 , H01L27/1157 , H01L27/11565 , H01L27/11551 , H01L27/11578
CPC分类号： H01L27/11286 , H01L21/02107 , H01L21/76801 , H01L21/76819 , H01L23/528 , H01L23/535 , H01L23/538 , H01L27/112 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

94. 发明申请

US20180323176A1 SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 审中-公开
公开(公告)号：US20180323176A1
公开(公告)日：2018-11-08
申请号：US16036413
申请日：2018-07-16
申请人： SK hynix Inc.
发明人： Kwan Dong KIM
IPC分类号： H01L25/065 , H01L23/00 , H01L27/112 , H01L27/108 , H01L27/11
CPC分类号： H01L25/0657 , H01L23/522 , H01L24/06 , H01L24/09 , H01L24/17 , H01L24/48 , H01L24/49 , H01L27/10897 , H01L27/1116 , H01L27/11286 , H01L2224/16146 , H01L2224/16235 , H01L2224/48145 , H01L2224/48227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548
摘要： A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips may be configured based on a load value of the semiconductor apparatus.

95. 发明授权

US09842802B2 Integrated circuit device featuring an antifuse and method of making same 有权
公开(公告)号：US09842802B2
公开(公告)日：2017-12-12
申请号：US14227415
申请日：2014-03-27
申请人： QUALCOMM Incorporated
发明人： Zhongze Wang , John Jianhong Zhu , Xia Li
IPC分类号： H01L21/82 , H01L27/112 , H01L21/8239 , H01L23/525 , G11C17/16 , H01L23/522 , H01L49/02
CPC分类号： H01L23/5252 , G11C17/16 , H01L23/5228 , H01L27/11206 , H01L27/11286 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.

96. 发明申请

US20170179027A1 MEMORY DEVICE HAVING CELL OVER PERIPHERY STRUCTURE AND MEMORY PACKAGE INCLUDING THE SAME 有权
公开(公告)号：US20170179027A1
公开(公告)日：2017-06-22
申请号：US15273268
申请日：2016-09-22
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： CHANG-BUM KIM , Sung-Hoon Kim
IPC分类号： H01L23/528 , H01L27/115
CPC分类号： H01L23/5283 , H01L25/072 , H01L27/11286 , H01L27/11519 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A memory device includes a substrate, and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.

97. 发明申请

US20170125404A1 SUPER CMOS DEVICES ON A MICROELECTRONICS SYSTEM 有权
公开(公告)号：US20170125404A1
公开(公告)日：2017-05-04
申请号：US15358049
申请日：2016-11-21
申请人： SCHOTTKY LSI, INC.
发明人： AUGUSTINE WEI-CHUN CHANG
IPC分类号： H01L27/06 , H01L27/112 , H01L31/07 , H01L21/8238 , H01L31/0376 , H01L27/11526 , H01L29/872
CPC分类号： H01L27/0629 , H01L21/8238 , H01L25/065 , H01L27/0207 , H01L27/0727 , H01L27/105 , H01L27/10897 , H01L27/112 , H01L27/11253 , H01L27/11286 , H01L27/11293 , H01L27/11526 , H01L27/11546 , H01L27/11807 , H01L28/20 , H01L29/66143 , H01L29/872 , H01L31/032 , H01L31/0376 , H01L31/03762 , H01L31/07 , H01L31/072 , H01L31/074 , H01L2924/0002 , H03K19/17728 , Y02E10/50 , H01L2924/00
摘要： This application is directed to a low cost IC solution that provides Super CMOS microelectronics macros. Hereinafter, SCMOS refers to Super CMOS and Schottky CMOS. SCMOS device solutions includes a niche circuit element, such as complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co, Ti, Ni or other metal atoms or compounds) to P- and N-Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form (i) generic logic gates, (ii) functional blocks of microprocessors and microcontrollers such as but not limited to data paths, multipliers, muliplier-accumaltors, (ii) memory cells and control circuits of various types (SRAM's with single or multiple read/write port(s), binary and ternary CAM's), (iii) multiplexers, crossbar switches, switch matrices in network processors, graphics processors and other processors to implement a variety of communication protocols and algorithms of data processing engines for (iv) Analytics, (v) block-chain and encryption-based security engines (vi) Artificial Neural Networks with specific circuits to emulate or to implement a self-learning data processor similar to or derived from the neurons and synapses of human or animal brains, (vii) analog circuits and functional blocks from simple to the complicated including but not limited to power conversion, control and management either based on charge pumps or inductors, sensor signal amplifiers and conditioners, interface drivers, wireline data transceivers, oscillators and clock synthesizers with phase and/or delay locked loops, temperature monitors and controllers; all the above are built from discrete components to all grades of VLSI chips. Solar photovoltaic electricity conversion, bio-lab-on-a-chip, hyperspectral imaging (capture/sensing and processing), wireless communication with various transceiver and/or transponder circuits for ranges of frequency that extend beyond a few 100 MHz, up to multi-THz, ambient energy harvesting either mechanical vibrations or antenna-based electromagnetic are newly extended or nacent fields of the SCMOS IC applications.

98. 发明申请

US20170117284A1 ONE-TIME PROGRAMMABLE MEMORY CELL CAPABLE OF REDUCING LEAKAGE CURRENT AND PREVENTING SLOW BIT RESPONSE, AND METHOD FOR PROGRAMMING A MEMORY ARRAY COMPRISING THE SAME 审中-公开
公开(公告)号：US20170117284A1
公开(公告)日：2017-04-27
申请号：US15399760
申请日：2017-01-06
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Wei-Zhe Wong , Hsin-Ming Chen
IPC分类号： H01L27/112 , G11C17/18 , G11C17/16 , H01L23/525 , H01L29/78
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/11286 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

99. 发明授权

US09601499B2 One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and method for programming a memory array comprising the same 有权
公开(公告)号：US09601499B2
公开(公告)日：2017-03-21
申请号：US15005012
申请日：2016-01-25
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Wei-Zhe Wong , Hsin-Ming Chen
IPC分类号： G11C17/14 , H01L27/112 , G11C17/16 , H01L29/78 , H01L27/10 , G11C17/18 , H01L23/525
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/11286 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

100. 发明授权

US09590052B2 High-voltage transistor having shielding gate 有权
标题翻译：具有屏蔽门的高电压晶体管
公开(公告)号：US09590052B2
公开(公告)日：2017-03-07
申请号：US14150366
申请日：2014-01-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L29/40 , H01L27/115 , H01L27/105 , H01L27/112
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译：半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。

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