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91. 发明授权

US5027172A Dynamic random access memory cell and method of making thereof 失效
标题翻译：动态随机存取存储单元及其制造方法
公开(公告)号：US5027172A
公开(公告)日：1991-06-25
申请号：US451775
申请日：1989-12-18
申请人： Jun-Young Jeon
发明人： Jun-Young Jeon
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1085 , H01L27/10835
摘要： A method of making a DRAM cell capable of increaisng storage capacity and for which is amendable to large-scale integration. The method provides a DRAM cell having stacked and trench capacitors and a transistor of second conductivity type opposite to a first conductivity type on a semiconductor substrate of the first conductivity type. Polycrystalline silicon of a cell node in the stack capacitor is coupled to source region of the transistor. The cell node of the trench capacitor is coupled to the source region of the transistor through an N-type diffusion region around the trench that is formed between said source region and a field oxide. Over the trench capacitor is disposed the stacked capacitor, and the cell nodes are coupled to each other. A cell plate filling the inside of the trench may be used in common since it surrounds the polycrystalline silicon, that is, the cell node of the stacked capacitor.
摘要翻译：制造能够增加存储容量的DRAM单元的方法，其可修改为大规模集成。该方法提供具有层叠和沟槽电容器的DRAM单元和在第一导电类型的半导体衬底上与第一导电类型相反的第二导电类型的晶体管。堆叠电容器中的单元节点的多晶硅耦合到晶体管的源极区域。沟槽电容器的单元节点通过形成在所述源极区域和场氧化物之间的沟槽周围的N型扩散区域耦合到晶体管的源极区域。在沟槽电容器上设置堆叠的电容器，并且单元节点彼此耦合。填充沟槽内部的电池板可以共同使用，因为它围绕多晶硅，即堆叠电容器的电池节点。

92. 发明授权

US4962476A Semiconductor memory device having bit lines less liable to have influences of the adjacent bit lines 失效
标题翻译：具有不易受相邻位线影响的位线的半导体存储器件
公开(公告)号：US4962476A
公开(公告)日：1990-10-09
申请号：US383397
申请日：1989-07-21
申请人： Koji Kawada
发明人： Koji Kawada
IPC分类号： H01L21/314 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L27/10 , H01L27/108
CPC分类号： H01L23/5283 , H01L23/5225 , H01L27/10808 , H01L27/10835 , H01L2924/0002
摘要： A semiconductor memory device according to the present invention has a plurality of memory cells of the one-transistor and one-capacitor type, and a plurality of bit lines coupled to columns of the memory cells, respectively, and disposed in an insulating film over the memory cells, and a common upper electrode is shared by the storage capacitors of the memory cells and has shield portions interposed between the bit lines, so that the adjacent bit lines are less liable to be capacitively coupled by virtue of the shield portions, thereby allowing data bit signals to propagate without any undesirable influence of the adjacent bit lines.

93. 发明授权

US4794563A Semiconductor memory device having a high capacitance storage capacitor 失效
标题翻译：具有高电容存储电容器的半导体存储器件
公开(公告)号：US4794563A
公开(公告)日：1988-12-27
申请号：US925547
申请日：1986-10-31
申请人： Satoshi Maeda
发明人： Satoshi Maeda
IPC分类号： H01L27/10 , G11C11/34 , H01L21/8242 , H01L27/108 , H01L29/08 , H01L29/94 , G11C11/24 , H01L29/78 , H01L27/02
CPC分类号： H01L27/10852 , H01L27/10808 , H01L27/10835 , H01L29/0847 , H01L29/945
摘要： This invention provides a semiconductor memory device for an integrated circuit comprising a semiconductor substrate of a first conductivity type, a field insulation layer on the semiconductor substrate, and a switch. This switch includes a gate insulation layer, a gate electrode on the gate insulation layer, and a pair of impurity regions of a second conductivity type in the substrate adjacent to the gate electrode. The device also includes a capacitor including a first electrode connected to one impurity region, a second electrode connected to a predetermined voltage, insulation means for separating the first and second electrodes, and groove means extending into the substrate for increasing the capacitace area of the first electrode.A method for making the devices is also described.
摘要翻译：本发明提供一种用于集成电路的半导体存储器件，其包括第一导电类型的半导体衬底，半导体衬底上的场绝缘层和开关。该开关包括栅极绝缘层，栅极绝缘层上的栅极电极和与栅电极相邻的基板中的第二导电类型的一对杂质区域。该器件还包括电容器，其包括连接到一个杂质区的第一电极，连接到预定电压的第二电极，用于分离第一和第二电极的绝缘装置以及延伸到衬底中的沟槽装置，以增加第一和第二电极的电容面积电极。还描述了用于制造这些装置的方法。

94. 发明授权

US09214467B2 Method for fabricating capacitor 有权
标题翻译：制造电容器的方法
公开(公告)号：US09214467B2
公开(公告)日：2015-12-15
申请号：US14604475
申请日：2015-01-23
申请人： SK hynix Inc.
发明人： Jin-Hyock Kim , Seung-Jin Yeom , Ki-Seon Park , Han-Sang Song , Deok-Sin Kil , Jae-Sung Roh
IPC分类号： H01L27/108 , H01L21/8239 , H01L49/02
CPC分类号： H01L27/10844 , H01L21/8239 , H01L27/10808 , H01L27/10835 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/60 , H01L28/65 , H01L28/91
摘要： A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.
摘要翻译：一种制造电容器的方法包括：在衬底上形成存储节点接触插塞; 形成绝缘层，其具有使存储节点接触插塞的表面暴露在存储接触插塞上的开口; 通过在不同温度下执行的两个步骤，在绝缘层和存储节点接触插塞的暴露表面上形成用于存储节点的导电层; 执行隔离工艺以隔离导电层的部分; 并在隔离的导电层上依次形成电介质层和平板电极。

95. 发明授权

US09059029B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09059029B2
公开(公告)日：2015-06-16
申请号：US13782704
申请日：2013-03-01
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yasuyuki Arai
IPC分类号： H01L27/108 , H01L27/115
CPC分类号： H01L29/7869 , H01L21/8239 , H01L27/108 , H01L27/10832 , H01L27/10835 , H01L27/1156 , H01L29/42392 , H01L29/66742 , H01L29/78696
摘要： To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided.
摘要翻译：提供高度集成的半导体存储器件。提供即使在不提供电力的情况下也能够保存存储的数据的半导体存储器件。提供具有大量写入周期的半导体存储器件。通过形成包括三维布置的两个晶体管和一个电容器的存储单元来增加存储单元阵列的积分度。使用具有比硅更宽的带隙的宽间隙半导体，通过形成用于控制存储单元中的电容器的电荷量的晶体管，防止积蓄在电容器中的电荷泄漏。因此，可以提供即使在未提供电力的情况下也可以保存存储的数据的半导体存储器件。

96. 发明授权

US08866208B2 Semiconductor devices including vertical transistors and methods of fabricating the same 有权
标题翻译：包括垂直晶体管的半导体器件及其制造方法
公开(公告)号：US08866208B2
公开(公告)日：2014-10-21
申请号：US13719100
申请日：2012-12-18
申请人： SK hynix Inc.
发明人： Jin Yul Lee
IPC分类号： H01L27/108 , H01L29/94 , H01L49/02
CPC分类号： H01L29/945 , H01L27/10835 , H01L27/10885 , H01L28/90
摘要： A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region.
摘要翻译：半导体器件包括在半导体衬底的沟槽中的第一电容器和设置在与第一电容器相对的半导体衬底上的有源柱。有源支柱包括依次层叠的第一区域，第一沟道区域，第二区域，第二沟道区域和第三区域。柱连接图案将第一电容器电连接到第一源极区域。第一栅电极设置在第一沟道区的侧壁上。公共漏极区域设置在第二区域中，公共位线设置在公共漏极区域的侧壁上。第二栅电极设置在第二沟道区的侧壁上，第二源区设置在第三区中。第二电容器设置在与第二通道区域相对的第二源极区域的顶表面上。

97. 发明申请

US20140035018A1 SEMICONDUCTOR DEVICES INCLUDING VERTICAL TRANSISTORS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：包括垂直晶体管的半导体器件及其制造方法
公开(公告)号：US20140035018A1
公开(公告)日：2014-02-06
申请号：US13719100
申请日：2012-12-18
申请人： SK HYNIX INC.
发明人： Jin Yul LEE
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/10835 , H01L27/10885 , H01L28/90
摘要： A semiconductor device includes a first capacitor in a trench of a semiconductor substrate and an active pillar disposed on the semiconductor substrate opposite the first capacitor. The active pillar includes first region, first channel region, second region, second channel region and third region, sequentially stacked. A pillar connection pattern electrically connects the first capacitor to a first source region. A first gate electrode is disposed on a sidewall of the first channel region. A common drain region is disposed in the second region, and a common bit line is disposed on a sidewall of the common drain region. A second gate electrode is disposed on a sidewall of the second channel region, and a second source region is disposed in the third region. A second capacitor is disposed on a top surface of the second source region opposite the second channel region.
摘要翻译：半导体器件包括在半导体衬底的沟槽中的第一电容器和设置在与第一电容器相对的半导体衬底上的有源柱。有源支柱包括依次层叠的第一区域，第一沟道区域，第二区域，第二沟道区域和第三区域。柱连接图案将第一电容器电连接到第一源极区域。第一栅电极设置在第一沟道区的侧壁上。公共漏极区域设置在第二区域中，公共位线设置在公共漏极区域的侧壁上。第二栅电极设置在第二沟道区的侧壁上，第二源区设置在第三区中。第二电容器设置在与第二通道区域相对的第二源极区域的顶表面上。

98. 发明申请

US20130228839A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130228839A1
公开(公告)日：2013-09-05
申请号：US13782704
申请日：2013-03-01
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Yasuyuki Arai
IPC分类号： H01L27/108
CPC分类号： H01L29/7869 , H01L21/8239 , H01L27/108 , H01L27/10832 , H01L27/10835 , H01L27/1156 , H01L29/42392 , H01L29/66742 , H01L29/78696
摘要： To provide a highly integrated semiconductor memory device. To provide a semiconductor memory device which can hold stored data even when power is not supplied. To provide a semiconductor memory device which has a large number of write cycles. The degree of integration of a memory cell array is increased by forming a memory cell including two transistors and one capacitor which are arranged three-dimensionally. The electric charge accumulated in the capacitor is prevented from being leaking by forming a transistor for controlling the amount of electric charge of the capacitor in the memory cell using a wide-gap semiconductor having a wider band gap than silicon. Accordingly, a semiconductor memory device which can hold stored data even when power is not supplied can be provided.

99. 发明授权

US07498207B2 Semiconductor memory device and manufacturing method of the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07498207B2
公开(公告)日：2009-03-03
申请号：US11902996
申请日：2007-09-27
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
摘要翻译：在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。

100. 发明申请

US20080023743A1 Semiconductor memory device and manufacturing method of the same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20080023743A1
公开(公告)日：2008-01-31
申请号：US11905002
申请日：2007-09-27
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L27/108
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
摘要翻译：在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。

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