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91. 发明授权

US07969015B2 Inverse chip connector 有权
标题翻译：反芯片连接器
公开(公告)号：US07969015B2
公开(公告)日：2011-06-28
申请号：US11329875
申请日：2006-01-10
申请人： John Trezza
发明人： John Trezza
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/11 , H01L21/4853 , H01L21/6835 , H01L21/76898 , H01L23/427 , H01L23/48 , H01L23/481 , H01L23/488 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68345 , H01L2221/68363 , H01L2221/68368 , H01L2223/6616 , H01L2223/6622 , H01L2224/02372 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/11912 , H01L2224/13012 , H01L2224/13021 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/1358 , H01L2224/136 , H01L2224/13609 , H01L2224/16146 , H01L2224/16237 , H01L2224/24226 , H01L2224/45111 , H01L2224/75 , H01L2224/75305 , H01L2224/81001 , H01L2224/81011 , H01L2224/81054 , H01L2224/81136 , H01L2224/81193 , H01L2224/81203 , H01L2224/81204 , H01L2224/81825 , H01L2224/81894 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06524 , H01L2225/06531 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01S5/02272 , H01S5/02276 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/18308 , H01S2301/176 , H01L2924/00014 , H01L2924/00
摘要： A system for connecting a first chip to a second chip having a post on the first chip having a first metallic material, a recessed wall within the second chip and defining a well within the second chip, a conductive diffusion layer material on a surface of the recessed wall within the well, and a malleable electrically conductive material on the post, the post being dimensioned for insertion into the well such that the malleable electrically conductive material will deform within the well and, upon heating to at least a tack temperature for the malleable, electrically conductive material, will form an electrically conductive tack connection with the diffusion layer to create an electrically conductive path between the first chip and the second chip.
摘要翻译：一种用于将第一芯片连接到具有第一芯片上的柱的第二芯片的系统，具有第一金属材料，第二芯片内的凹陷壁，并且在第二芯片内限定阱，在所述第二芯片的表面上的导电扩散层材料凹陷的壁，以及位于柱上的可延展的导电材料，该柱的尺寸被设计成用于插入到井中，使得可延展的导电材料将在孔内变形，并且在加热至至少一个粘性温度用于可延展的导电材料将形成与扩散层的导电粘性连接，以在第一芯片和第二芯片之间形成导电路径。

92. 发明申请

US20100123268A1 Printing Semiconductor Elements by Shear-Assisted Elastomeric Stamp Transfer 有权
标题翻译：通过剪切辅助弹性印章印刷印刷半导体元件
公开(公告)号：US20100123268A1
公开(公告)日：2010-05-20
申请号：US12621804
申请日：2009-11-19
申请人： Etienne MENARD
发明人： Etienne MENARD
IPC分类号： B28B11/08 , B29C59/00
CPC分类号： H01L21/6835 , H01L21/67092 , H01L24/75 , H01L24/83 , H01L24/97 , H01L2221/68354 , H01L2224/75303 , H01L2224/75305 , H01L2224/75315 , H01L2224/7598 , H01L2224/83192 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/10329 , H01L2924/10336 , H01L2924/10349 , H01L2924/12041 , H01L2924/14 , H01L2924/15788 , H01L2924/01014 , H01L2924/01015 , H01L2924/01049 , H01L2924/01031 , H01L2924/01051 , H01L2924/00
摘要： Provided are methods and devices for transfer printing of semiconductor elements to a receiving surface. In an aspect, the printing is by conformal contact between an elastomeric stamp inked with the semiconductor elements and a receiving surface, and during stamp removal, a shear offset is applied between the stamp and the receiving surface. The shear-offset printing process achieves high printing transfer yields with good placement accuracy. Process parameter selection during transfer printing, including time varying stamp-backing pressure application and vertical displacement, yields substantially constant delamination rates with attendant transfer printing improvement.
摘要翻译：提供了用于将半导体元件转印到接收表面的方法和装置。在一个方面，打印是通过在与半导体元件和接收表面之间着墨的弹性体印章之间的共形接触，并且在印模移除期间，在印模和接收表面之间施加剪切偏移。剪切胶版印刷工艺实现了高印刷转印率，具有良好的定位精度。转印期间的工艺参数选择，包括随时间变化的背压压力施加和垂直位移，产生基本上恒定的分层率，伴随着转印打印的改进。

93. 发明授权

US07659182B2 Method of wafer-to-wafer bonding 失效
标题翻译：晶圆到晶圆键合的方法
公开(公告)号：US07659182B2
公开(公告)日：2010-02-09
申请号：US11804863
申请日：2007-05-21
申请人： Vladimir Vaganov , Nickolai Belov
发明人： Vladimir Vaganov , Nickolai Belov
IPC分类号： H01L21/00
CPC分类号： H01L21/4803 , B30B15/061 , B81C1/0038 , B81C2201/019 , B81C2203/038 , H01L21/2007 , H01L21/4857 , H01L2224/75305 , H01L2224/75314 , H01L2224/7598 , H01L2924/01322 , H01L2924/09701 , H01L2924/1461 , H01L2924/00
摘要： Methods of wafer-to-wafer bonding are disclosed. These methods use a force-transposing substrate providing redistribution of the applied force to the local bonding areas across the wafer. Certain versions of the Present Invention also provide a compliant force-distributing member along with applying bonding material to bonding areas in select locations. A predetermined sequence of external force loading and temperature steps ensure creating bonds between the wafers in the bonding areas. The disclosed methods improve wafer bonding, by increasing its uniformity and strength across the wafer, increasing both reproducibility and yield process and decreasing cost of semiconductor and MEMS devices.
摘要翻译：公开了晶片到晶片结合的方法。这些方法使用强力转置衬底，其提供所施加的力再次分布到晶片上的局部结合区域。本发明的某些形式还提供顺应力分配构件以及将粘合材料施加到选择位置中的结合区域。外力加载和温度步骤的预定顺序确保在粘合区域中的晶片之间产生粘合。所公开的方法通过增加其在晶片上的均匀性和强度来提高晶片接合，提高了再现性和屈服过程，降低了半导体和MEMS器件的成本。

94. 发明授权

US07534722B2 Back-to-front via process 有权
标题翻译：通过过程进行背对背
公开(公告)号：US07534722B2
公开(公告)日：2009-05-19
申请号：US11329574
申请日：2006-01-10
申请人： John Trezza
发明人： John Trezza
IPC分类号： H01L21/44 , H01L21/4763 , H01L29/40 , H01L23/52 , H01L23/48 , H01L23/40
CPC分类号： H01L24/94 , H01L21/6835 , H01L21/76898 , H01L23/427 , H01L23/48 , H01L23/481 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/11 , H01L24/13 , H01L24/24 , H01L24/27 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68368 , H01L2223/6616 , H01L2223/6622 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/05026 , H01L2224/05027 , H01L2224/0508 , H01L2224/05147 , H01L2224/05568 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/1147 , H01L2224/13099 , H01L2224/13609 , H01L2224/16 , H01L2224/24226 , H01L2224/274 , H01L2224/75305 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01061 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
摘要： A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.
摘要翻译：在具有邻接衬底的掺杂半导体材料的半导体芯片上执行的方法包括通过从衬底的外侧向掺杂半导体材料延伸的至少部分衬底形成第一通孔，第一通孔具有壁表面和将第一导电材料引入第一通孔中以形成导电路径，从半导体芯片的掺杂部分的外表面延伸到底部，产生与第一通孔对准的第二通孔，并将第二导电材料引入第二通孔中，以便产生导电路径。

95. 发明授权

US07533792B2 Elastic interface for wafer bonding apparatus 有权
标题翻译：晶圆接合装置弹性界面
公开(公告)号：US07533792B2
公开(公告)日：2009-05-19
申请号：US11347219
申请日：2006-02-06
申请人： David M. Erlach
发明人： David M. Erlach
IPC分类号： B23K37/00
CPC分类号： H01L21/6835 , H01L21/2007 , H01L21/67092 , H01L2224/75305 , H01L2224/75314
摘要： An apparatus for bonding a lid wafer to a device wafer includes an elastic interface having a first surface and a second surface. Relieved areas may be created in the elastic interface by removing at least some of the elastic material of the interface, leaving a mesh with nodes. Raised areas may be disposed on the nodes in staggered positions on the first surface relative to the second surface. The bonding pressure deflects the raised features on the first surface in one direction and the raised features on the second surface in another direction. The restoring force of the mesh transmits the pressure through the interface and to a lid wafer and a device wafer, to bond the lid wafer to the device wafer.
摘要翻译：用于将盖晶片接合到器件晶片的装置包括具有第一表面和第二表面的弹性界面。可以通过移除界面中的至少一些弹性材料而在弹性界面中产生缓解区域，留下与节点的网格。凸起区域可以相对于第二表面设置在第一表面上的交错位置的节点上。接合压力使一个方向上的第一表面上的凸起特征偏转，并且在另一个方向上将第二表面上的凸起特征偏转。网的恢复力将压力通过界面传递到盖晶片和器件晶片，以将盖晶片结合到器件晶片。

96. 发明申请

US20080070376A1 Method of wafer-to-wafer bonding 失效
标题翻译：晶圆到晶圆键合的方法
公开(公告)号：US20080070376A1
公开(公告)日：2008-03-20
申请号：US11804863
申请日：2007-05-21
申请人： Vladimir Vaganov , Nickolai Belov
发明人： Vladimir Vaganov , Nickolai Belov
IPC分类号： H01L21/30
CPC分类号： H01L21/4803 , B30B15/061 , B81C1/0038 , B81C2201/019 , B81C2203/038 , H01L21/2007 , H01L21/4857 , H01L2224/75305 , H01L2224/75314 , H01L2224/7598 , H01L2924/01322 , H01L2924/09701 , H01L2924/1461 , H01L2924/00
摘要： Methods of wafer-to-wafer bonding are disclosed. These methods use a force-transposing substrate providing redistribution of the applied force to the local bonding areas across the wafer. Certain versions of the Present Invention also provide a compliant force-distributing member along with applying bonding material to bonding areas in selectable locations. A predetermined sequence of external force loading and temperature steps ensure creating bonds between the wafers in the bonding areas. The disclosed methods improve wafer bonding, by increasing its uniformity and strength across the wafer, increase both reproducibility and yield process and decrease cost of semiconductor and MEMS devices.
摘要翻译：公开了晶片到晶片结合的方法。这些方法使用强力转置衬底，其提供所施加的力再次分布到晶片上的局部结合区域。本发明的某些形式还提供顺应力分配构件以及将可能位置的结合区域施加粘合材料。外力加载和温度步骤的预定顺序确保在粘合区域中的晶片之间产生粘合。所公开的方法通过增加其在晶片上的均匀性和强度来改善晶片结合，增加了再现性和屈服过程，并降低了半导体和MEMS器件的成本。

97. 发明申请

US20070172987A1 MEMBRANE-BASED CHIP TOOLING 有权
标题翻译：基于膜的芯片工具
公开(公告)号：US20070172987A1
公开(公告)日：2007-07-26
申请号：US11693984
申请日：2007-03-30
申请人： Roger Dugas , John Trezza
发明人： Roger Dugas , John Trezza
IPC分类号： H01L21/00
CPC分类号： H01L24/11 , H01L21/4853 , H01L21/6835 , H01L21/76898 , H01L23/427 , H01L23/48 , H01L23/481 , H01L23/488 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68345 , H01L2221/68363 , H01L2221/68368 , H01L2223/6616 , H01L2223/6622 , H01L2224/02372 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/11912 , H01L2224/13012 , H01L2224/13021 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/1358 , H01L2224/136 , H01L2224/13609 , H01L2224/16146 , H01L2224/16237 , H01L2224/24226 , H01L2224/45111 , H01L2224/75 , H01L2224/75305 , H01L2224/81001 , H01L2224/81011 , H01L2224/81054 , H01L2224/81136 , H01L2224/81193 , H01L2224/81203 , H01L2224/81204 , H01L2224/81825 , H01L2224/81894 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06524 , H01L2225/06531 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01S5/02272 , H01S5/02276 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/18308 , H01S2301/176 , H01L2924/00014 , H01L2924/00
摘要： A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
摘要翻译：一种使用多个芯片的方法，每个芯片分别具有包括电触点的接合表面和与接合表面相对的一侧的表面，包括使位于主体上的可硬化材料与多个芯片接触，硬化可硬化材料，从而约束多个芯片中的每一个的至少一部分，将多个芯片从第一位置移动到第二位置，向身体施加力，使得硬化的可硬化材料将均匀地传递施加到身体的垂直力，以在每个单独的芯片的接合表面与第二位置处的单个芯片将被接合的元件的接合表面接触的同时，不会对各个芯片元件造成损害，，或粘结面。

98. 发明授权

US07150388B2 Method of bonding and bonding apparatus for a semiconductor chip 失效
标题翻译：半导体芯片的接合和接合装置的方法
公开(公告)号：US07150388B2
公开(公告)日：2006-12-19
申请号：US11022867
申请日：2004-12-28
申请人： Takayoshi Matsumura
发明人： Takayoshi Matsumura
IPC分类号： B23K1/06
CPC分类号： B23K20/10 , B23K2101/40 , H01L24/75 , H01L24/81 , H01L2224/16 , H01L2224/75 , H01L2224/75305 , H01L2224/81205 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01079
摘要： A method of bonding and a bonding apparatus for a semiconductor chip uses ultrasonic vibration but can improve the bonds between electrode terminals of a semiconductor chip and a substrate. In a method of bonding a semiconductor chip that places electrode terminals of the semiconductor chip and electrode terminals of a substrate in contact and applies ultrasonic vibration to the semiconductor chip to bond the electrode terminals of the semiconductor chip and the substrate together, the ultrasonic vibration is compressional waves that are transmitted to the semiconductor chip and is set so that a half-wavelength of the ultrasonic vibration is a length given by multiplying a gap between adjacent electrode terminals in a direction of the compressional waves by a reciprocal of a natural number, and maximum amplitude points are located at positions of the respective electrode terminals of the semiconductor chip and the substrate.
摘要翻译：用于半导体芯片的接合方法和接合装置使用超声波振动，但是可以改善半导体芯片的电极端子与基板之间的结合。在将半导体芯片的电极端子与基板的电极端子接触的半导体芯片接合的方法中，对半导体芯片施加超声波振动，将半导体芯片和基板的电极端子接合在一起，超声波振动为发送到半导体芯片的压缩波被设定为使得超声波振动的半波长是通过将相邻的电极端子之间的间隙沿着自然数的倒数乘以相邻的电极端子之间的间隔而给出的长度，以及最大幅度点位于半导体芯片和基板的各个电极端子的位置。

99. 发明申请

US20060281307A1 Post-attachment chip-to-chip connection 有权
公开(公告)号：US20060281307A1
公开(公告)日：2006-12-14
申请号：US11329873
申请日：2006-01-10
申请人： John Trezza
发明人： John Trezza
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L21/4853 , H01L21/6835 , H01L21/76898 , H01L23/427 , H01L23/48 , H01L23/481 , H01L23/488 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68345 , H01L2221/68363 , H01L2221/68368 , H01L2223/6616 , H01L2223/6622 , H01L2224/02372 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/11912 , H01L2224/13012 , H01L2224/13021 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/1358 , H01L2224/136 , H01L2224/13609 , H01L2224/16146 , H01L2224/16237 , H01L2224/24226 , H01L2224/45111 , H01L2224/75 , H01L2224/75305 , H01L2224/81001 , H01L2224/81011 , H01L2224/81054 , H01L2224/81136 , H01L2224/81193 , H01L2224/81203 , H01L2224/81204 , H01L2224/81825 , H01L2224/81894 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06524 , H01L2225/06531 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01S5/02272 , H01S5/02276 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/18308 , H01S2301/176 , H01L2924/00014 , H01L2924/00
摘要： A method of forming an electrical connection from a first chip, having a contact pad exposed through an opening in cover glass on the chip, to a second chip having a first side and a second side and involves attaching the second chip to the first chip, etching an annular via having an inner and outer perimeter, the inner perimeter corresponding to an outer perimeter of the contact pad, the annular via extending into and through the second chip and down to the cover glass such that the annular via's inner perimeter substantially corresponds to the contact pad's outer perimeter, filling the annular via with an insulator, removing semiconductor material of the second chip within the inner perimeter of the insulator to create a void extending from the second side to the contact pad, and filling at least some of the void with a conductive material.

100. 发明申请

US20060278988A1 Profiled contact 有权
标题翻译：联络人
公开(公告)号：US20060278988A1
公开(公告)日：2006-12-14
申请号：US11329481
申请日：2006-01-10
申请人： John Trezza , John Callahan , Gregory Dudoff
发明人： John Trezza , John Callahan , Gregory Dudoff
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L21/4853 , H01L21/6835 , H01L21/76898 , H01L23/427 , H01L23/48 , H01L23/481 , H01L23/488 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68345 , H01L2221/68363 , H01L2221/68368 , H01L2223/6616 , H01L2223/6622 , H01L2224/02372 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/11912 , H01L2224/13012 , H01L2224/13021 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/1358 , H01L2224/136 , H01L2224/13609 , H01L2224/16146 , H01L2224/16237 , H01L2224/24226 , H01L2224/45111 , H01L2224/75 , H01L2224/75305 , H01L2224/81001 , H01L2224/81011 , H01L2224/81054 , H01L2224/81136 , H01L2224/81193 , H01L2224/81203 , H01L2224/81204 , H01L2224/81825 , H01L2224/81894 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06524 , H01L2225/06531 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01S5/02272 , H01S5/02276 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/18308 , H01S2301/176 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor chip, having IC pads, the semiconductor chip having a device, electrically connected to at least one electrical contact through the IC pad, the electrical contact having a height and a cross sectional profile, through the height, configured to facilitate penetration of at least a portion of the electrical contact into a malleable contact on a second semiconductor chip.
摘要翻译：一种半导体芯片，其具有IC焊盘，所述半导体芯片具有与所述IC焊盘至少一个电触头电连接的器件，所述电触头具有穿过所述高度的高度和横截面轮廓，所述高度和横截面轮廓被构造成促进穿透在第二半导体芯片上的电触点的至少一部分成为可延展的触点。

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