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91. 发明申请

US20190108998A1 ENGINEERING OF FERROELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY SURFACE POTENTIAL MODULATION 审中-公开
公开(公告)号：US20190108998A1
公开(公告)日：2019-04-11
申请号：US15729815
申请日：2017-10-11
申请人： GLOBALFOUNDRIES Inc.
发明人： Lars Mueller-Meskamp , Stefan Duenkel
IPC分类号： H01L21/02 , H01L21/762 , H01L29/78 , H01L21/265 , H01L21/223 , H01L29/06 , H01L29/66
CPC分类号： H01L21/02299 , H01L21/02172 , H01L21/02181 , H01L21/2236 , H01L21/26506 , H01L21/76267 , H01L21/76283 , H01L29/0649 , H01L29/40111 , H01L29/516 , H01L29/66477 , H01L29/78391 , H01L29/7841
摘要： In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.

92. 发明授权

US10074716B2 Saucer-shaped isolation structures for semiconductor devices 有权
公开(公告)号：US10074716B2
公开(公告)日：2018-09-11
申请号：US14875176
申请日：2015-10-05
申请人： SKYWORKS SOLUTIONS (HONG KONG) LIMITED , ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
发明人： Wai Tien Chan , Donald Ray Disney , Richard K. Williams
IPC分类号： H01L21/70 , H01L29/06 , H01L21/265 , H01L21/761 , H01L21/762 , H01L21/763 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： An isolation structure formed in a semiconductor substrate of a first conductivity type includes a region of a second conductivity type opposite to the first conductivity type. The region of the second conductivity type is saucer-shaped and has a floor portion substantially parallel to the top surface of the substrate and a sloped sidewall portion. The sloped sidewall portion extends downward from the top surface of the substrate at an oblique angle and merges with the floor portion. The floor portion and the sloped sidewall portion together form an isolated pocket of the substrate.

93. 发明申请

US20160351439A1 ASPECT RATIO FOR SEMICONDUCTOR ON INSULATOR 有权
公开(公告)号：US20160351439A1
公开(公告)日：2016-12-01
申请号：US14725400
申请日：2015-05-29
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L21/762 , H01L21/3213 , H01L29/06 , H01L21/3205
CPC分类号： H01L21/845 , H01L21/3081 , H01L21/31111 , H01L21/32055 , H01L21/32134 , H01L21/76267 , H01L21/76283 , H01L21/823431 , H01L27/1211 , H01L29/0649 , H01L29/0657 , H01L29/165 , H01L29/20 , H01L29/41791 , H01L29/66795 , H01L29/7831
摘要： A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate. The insulated substrate comprising a silicon substrate, and an insulator layer deposited on the silicon substrate. The one or more fins in the first region comprising a first material layer deposited on the insulator layer. The one or more fins in the second region comprising a second material layer deposited on the insulator layer.

94. 发明申请

US20160329349A1 COMPACT SELF-ALIGNED IMPLANTATION TRANSISTOR EDGE RESISTOR FOR SRAM SEU MITIGATION 有权
标题翻译：用于SRAM SEU减缓的紧凑的自对准植入半导体边缘电阻
公开(公告)号：US20160329349A1
公开(公告)日：2016-11-10
申请号：US14705778
申请日：2015-05-06
申请人： Honeywell International Inc.
发明人： Paul S. Fechner
IPC分类号： H01L27/12 , H01L49/02 , H01L21/762 , H01L29/06
CPC分类号： H01L27/1203 , H01L21/26513 , H01L21/26586 , H01L21/76267 , H01L21/76283 , H01L27/0738 , H01L27/0883 , H01L28/20 , H01L29/0649 , H01L29/1041 , H01L29/1045 , H01L29/66166 , H01L29/78606 , H01L29/8605
摘要： This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby fortning a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator adjacent to the resistor, removing the barrier, and forming agate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.
摘要翻译：本公开涉及用于制造具有通过自对准倾斜注入形成在晶体管阱侧壁边缘上的具有电阻器的SRAM单元的CMOS器件的技术，其可以实现具有SEU缓解的更紧凑的SRAM架构，例如用于基于空间或其它辐射 - 硬化应用。一种示例性方法包括将掺杂剂注入掺杂的半导体阱中，所述掺杂半导体阱被势垒覆盖，其中所述掺杂半导体阱设置在掩埋绝缘体上，并且其中所述掺杂剂与所述掺杂半导体阱具有相反的掺杂类型，从而在边缘上形成电阻器的掺杂半导体阱，其中电阻器具有相反的掺杂类型。该方法还包括形成与电阻器相邻的第二绝缘体，去除阻挡层，以及在掺杂半导体阱上形成玛瑙层，由此形成与掺杂半导体阱和电阻器相邻的栅极。

95. 发明授权

US09373694B2 System and method for integrated circuits with cylindrical gate structures 有权
标题翻译：具有圆柱形栅极结构的集成电路的系统和方法
公开(公告)号：US09373694B2
公开(公告)日：2016-06-21
申请号：US13848707
申请日：2013-03-21
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
发明人： De Yuan Xiao , Guo Qing Chen , Roger Lee , Chin Fu Yen , Su Xing , Xiao Lu Huang , Yong Sheng Yang
IPC分类号： H01L29/66 , H01L29/78 , B82Y10/00 , H01L29/423 , H01L29/786 , H01L29/06 , B82Y40/00 , H01L29/775 , B82Y20/00
CPC分类号： H01L21/32133 , B82Y10/00 , B82Y20/00 , B82Y40/00 , H01L21/26506 , H01L21/30604 , H01L21/32139 , H01L21/324 , H01L21/76267 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66477 , H01L29/66795 , H01L29/775 , H01L29/78 , H01L29/7854 , H01L29/78696
摘要： A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.
摘要翻译：公开了一种具有周围栅极结构的集成电路的装置和方法。该器件在半导体衬底上包括半导体衬底和鳍状结构。鳍结构掺杂有第一导电类型，并且包括在一个远端处的源极区域和在相对的远端处的漏极区域。该器件还包括覆盖设置在鳍结构的源极和漏极区域之间的沟道区的栅极结构。翅片结构具有矩形横截面底部和拱形横截面顶部。拱形横截面顶部是半圆形的并且具有等于或小于矩形横截面底部部分的高度的半径。源极，漏极和沟道区域各自掺杂相同极性和相同浓度的掺杂剂。

96. 发明授权

US09257504B2 Isolation structures for semiconductor devices 有权
标题翻译：半导体器件的隔离结构
公开(公告)号：US09257504B2
公开(公告)日：2016-02-09
申请号：US14281075
申请日：2014-05-19
申请人： ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED , SKYWORKS SOLUTIONS (HONG KONG) LIMITED
发明人： Wai Tien Chan , Donald Ray Disney , Richard Kent Williams
IPC分类号： H01L21/70 , H01L29/06 , H01L21/265 , H01L21/761 , H01L21/762 , H01L21/763 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： Isolation structures for isolating semiconductor devices from a substrate include floor isolation regions buried within the substrate and one or more trenches extending from a surface of the substrate to the buried floor isolation region.
摘要翻译：用于从衬底隔离半导体器件的隔离结构包括掩埋在衬底内的底部隔离区域和从衬底的表面延伸到掩埋地板隔离区域的一个或多个沟槽。

97. 发明申请

US20160027869A1 SAUCER-SHAPED ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于半导体器件的SAUCER-SHAPED隔离结构
公开(公告)号：US20160027869A1
公开(公告)日：2016-01-28
申请号：US14875176
申请日：2015-10-05
申请人： ADVANCED ANALOGIC TECHNOLOGIES (HONG KONG) LIMITED , ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
发明人： Wai Tien Chan , Donald Ray Disney , Richard Kent Williams
IPC分类号： H01L29/06 , H01L21/762 , H01L21/761
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： An isolation structure formed in a semiconductor substrate of a first conductivity type includes a region of a second conductivity type opposite to the first conductivity type. The region of the second conductivity type is saucer-shaped and has a floor portion substantially parallel to the top surface of the substrate and a sloped sidewall portion. The sloped sidewall portion extends downward from the top surface of the substrate at an oblique angle and merges with the floor portion. The floor portion and the sloped sidewall portion together form an isolated pocket of the substrate.
摘要翻译：形成在第一导电类型的半导体衬底中的隔离结构包括与第一导电类型相反的第二导电类型的区域。第二导电类型的区域是碟形，并且具有基本上平行于基板的顶表面的底部部分和倾斜的侧壁部分。倾斜的侧壁部分以斜角从基板的顶表面向下延伸并与底板部分合并。地板部分和倾斜的侧壁部分一起形成基板的隔离袋。

98. 发明申请

US20150294901A1 LOCALIZED REGION OF ISOLATED SILICON OVER RECESSED DIELECTRIC LAYER 有权
标题翻译：隔离介质层隔离硅的局部化区域
公开(公告)号：US20150294901A1
公开(公告)日：2015-10-15
申请号：US14301765
申请日：2014-06-11
申请人： Texas Instruments Incorporated
发明人： Daniel Nelson Carothers , Jeffrey R. Debord
IPC分类号： H01L21/762 , H01L21/84 , H01L21/3105 , H01L21/02 , H01L21/306
CPC分类号： H01L21/76267 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/02532 , H01L21/0262 , H01L21/02667 , H01L21/30604 , H01L21/30625 , H01L21/3065 , H01L21/3081 , H01L21/31053 , H01L21/31055 , H01L21/76224 , H01L21/76262 , H01L21/76281 , H01L21/84
摘要： An integrated circuit is formed by forming an isolation recess in a single crystal substrate which includes silicon, filling the isolation recess with isolation dielectric material, and planarizing the isolation dielectric material to be coplanar with the top surface of the substrate to form a buried isolation layer. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on exposed areas of the substrate and polycrystalline or amorphous silicon-based material on the buried isolation layer. A cap layer is formed over the epitaxial silicon-based material, and a radiantly-induced recrystallization process causes the polycrystalline or amorphous silicon-based material to form single-crystalline semiconductor over the buried isolation layer.
摘要翻译：通过在包括硅的单晶衬底中形成隔离凹槽来形成集成电路，用隔离电介质材料填充隔离凹槽，以及将隔离电介质材料平坦化以与衬底的顶表面共面以形成掩埋隔离层。非选择性外延工艺在衬底的暴露区域和掩埋隔离层上的多晶或非晶硅基材料上形成单晶硅基半导体材料。在外延硅基材料上形成覆盖层，并且辐射诱导的再结晶过程使多晶或非晶硅基材料在掩埋隔离层上形成单晶半导体。

99. 发明申请

US20150263041A1 MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE 有权
公开(公告)号：US20150263041A1
公开(公告)日：2015-09-17
申请号：US14696736
申请日：2015-04-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Bruce B. Doris , Pranita Kerber , Ali Khakifirooz
IPC分类号： H01L27/12 , H01L29/45 , H01L29/78
CPC分类号： H01L27/1203 , H01L21/2652 , H01L21/26586 , H01L21/76267 , H01L21/84 , H01L29/45 , H01L29/66772 , H01L29/7831 , H01L29/78648
摘要： An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

100. 发明授权

US09105577B2 MOSFET with work function adjusted metal backgate 有权
标题翻译：具有工作功能的MOSFET调节金属后盖
公开(公告)号：US09105577B2
公开(公告)日：2015-08-11
申请号：US13398151
申请日：2012-02-16
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/336 , H01L21/265 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/2652 , H01L21/26586 , H01L21/76267 , H01L21/84 , H01L29/45 , H01L29/66772 , H01L29/7831 , H01L29/78648
摘要： An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.
摘要翻译： SOI衬底，半导体器件和背栅功函数调谐方法。衬底和器件具有多个金属背栅区域，其中至少两个区域具有不同的功函数。该方法包括在衬底上形成掩模并且注入置于衬底氧化物和衬底的体区之间的金属背栅，从而产生具有不同剂量的杂质和不同功函数的至少两个金属背栅区。工作功能区域可以对准，使得每个晶体管具有不同的阈值电压。当顶栅电极用作掩模时，形成在沟道区下具有第一功函数的金属背栅和源/漏区下的第二功函数。植入物可以倾斜以相对于掩模移动功函数区域。

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