专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20150006855A1 PREDICTIVE FETCHING AND DECODING FOR SELECTED INSTRUCTIONS 有权
公开(公告)号：US20150006855A1
公开(公告)日：2015-01-01
申请号：US13931656
申请日：2013-06-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/30054 , G06F9/30058 , G06F9/30145 , G06F9/3016 , G06F9/3806 , G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： Predictive fetching and decoding for selected instructions (e.g., operating system instructions, hypervisor instructions or other such instructions). A determination is made that a selected instruction, such as a system call instruction, an asynchronous interrupt, a return from system call instruction or return from asynchronous interrupt, is to be executed. Based on determining that such an instruction is to be executed, a predicted address is determined for the selected instruction, which is the address to which processing transfers in order to provide the requested services. Then, fetching of instructions beginning at the predicted address prior to execution of the selected instruction is commenced. Further, speculative state relating to a selected instruction, including, for instance, an indication of the privilege level of the selected instruction or instructions executed on behalf of the selected instruction, is predicted and maintained.

92. 发明授权

US08922568B2 Switching between dedicated function hardware and use of a software routine to generate result data 有权
标题翻译：在专用功能硬件之间切换并使用软件程序生成结果数据
公开(公告)号：US08922568B2
公开(公告)日：2014-12-30
申请号：US13067570
申请日：2011-06-09
申请人： Simon Jones , Andreas Engh-Halstvedt , Aske Simon Christensen
发明人： Simon Jones , Andreas Engh-Halstvedt , Aske Simon Christensen
IPC分类号： G06T1/00 , G06F13/14 , G06F7/38 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30189 , G06F9/30058 , G06F9/30145 , G06F9/3877
摘要： An apparatus for processing data 2 is provided including processing circuitry 24 controlled by an instruction decoder 20 in response to a stream of program instructions. There is also provided dedicated function hardware 12 configured to receive output data from the processing circuitry and to perform a dedicated processing operation. The instruction decoder 20 is responsive to an end instruction 54 and a software processing flag (blend_shade_enabled) to control the processing circuitry to end a current software routine, to generate output data and in dependence upon the software processing flag either trigger processing of the output data by the dedicated function hardware or trigger the processing circuitry to perform a further software routine upon the output data to generate software generated result data instead of hardware generated result data as generated by the dedicated hardware circuitry.
摘要翻译：提供了一种用于处理数据2的装置，其包括响应于程序指令流由指令解码器20控制的处理电路24。还提供了专用功能硬件12，其被配置为从处理电路接收输出数据并执行专用处理操作。指令解码器20响应于结束指令54和软件处理标志（blend_shade_enabled）来控制处理电路以结束当前软件程序，以产生输出数据，并根据软件处理标志触发输出数据的处理通过专用功能硬件或触发处理电路，以在输出数据上执行另外的软件程序以产生软件产生的结果数据，而不是由专用硬件电路产生的硬件产生的结果数据。

93. 发明授权

US08914622B2 Processor testing 有权
标题翻译：处理器测试
公开(公告)号：US08914622B2
公开(公告)日：2014-12-16
申请号：US13460413
申请日：2012-04-30
申请人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/32 , G06F11/22 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30058 , G06F9/3005 , G06F9/3804 , G06F11/2236 , G06F11/28
摘要： Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
摘要翻译：处理器可以根据各种实现来测试。在一般的实现中，用于处理器测试的过程可以包括为指令集的第一部分随机生成第一多个分支指令，第一部分中的每个分支指令分支到指令集的第二部分中的相应指令，分支指令的分支到相应的指令以顺序的方式排列。该过程还可以包括随机生成用于指令集的第二部分的第二多个分支指令，第二部分中的每个分支指令分支到指令集的第一部分中的相应指令，分支指令分支到相应的指令按顺序排列。该过程可以另外包括在执行期间遇到每个分支指令时产生多个指令来增加计数器。

94. 发明申请

US20140351561A1 MICROPROCESSOR THAT FUSES IF-THEN INSTRUCTIONS 有权
标题翻译：如果说明说明书的话，MICROPROCESSOR FUSES
公开(公告)号：US20140351561A1
公开(公告)日：2014-11-27
申请号：US14066520
申请日：2013-10-29
申请人： VIA TECHNOLOGIES, INC.
发明人： Terry Parks , G. Glenn Henry
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3836
摘要： A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.
摘要翻译：微处理器包括指令翻译单元，其从IT指令中提取条件信息，并使IT指令与第一IT块指令融合。对于IT块的每个指令，指令转换单元使用从IT指令提取的条件信息来确定IT块指令的相应条件，并将IT块指令转换成微指令。微指令包括各自的条件。执行单元根据各自的条件有条件地执行微指令。对于每个IT块指令，指令转换单元使用提取的条件信息来确定各自的状态值。状态值包括具有左移N-1位的低5位的IT指令的低8位，其中N表示IT块指令在IT块中的位置。

95. 发明授权

US08887002B2 Transactional execution branch indications 有权
标题翻译：交易执行分支指示
公开(公告)号：US08887002B2
公开(公告)日：2014-11-11
申请号：US13783366
申请日：2013-03-03
申请人： International Business Machines Corporation
发明人： Dan F. Greiner , Christian Jacobi , Donald W. Schmidt , Timothy J. Slegel
IPC分类号： G06F11/00 , G06F9/30 , G06F9/46 , G06F11/36
CPC分类号： G06F9/30058 , G06F9/30087 , G06F9/466 , G06F11/366
摘要： Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as a result of executing a branch instruction within the transaction. As the transaction executes and a branch instruction is encountered, a branch indication is set in a vector indicating whether the branch was taken. Then, if the transaction aborts, the indicators are stored in one or more transaction diagnostic blocks providing a branch history usable in diagnosing the failure.
摘要翻译：当事务被中止时，事务执行分支指示被放置到一个或多个事务诊断块中。作为在事务中执行分支指令的结果，每个分支指示指定是否采用分支。当事务执行并且遇到分支指令时，在指示是否采取分支的向量中设置分支指示。然后，如果事务中止，则指示符存储在提供可用于诊断故障的分支历史的一个或多个事务诊断块中。

96. 发明申请

US20140281394A1 METHOD TO IMPROVE SPEED OF EXECUTING RETURN BRANCH INSTRUCTIONS IN A PROCESSOR 有权
标题翻译：在处理器中提高执行返回分支指令速度的方法
公开(公告)号：US20140281394A1
公开(公告)日：2014-09-18
申请号：US13833844
申请日：2013-03-15
申请人： QUALCOMM INCORPORATED
发明人： Rodney Wayne Smith , Jeffery M. Schottmiller , Michael Scott McIlvaine , Brian Michael Stempel , Melinda J. Brown , Daren Eugene Streett
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/30054 , G06F9/3806
摘要： An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness.
摘要翻译：一种用于通过利用链路寄存器堆栈在处理器中执行呼叫分支和返回分支指令的装置和方法。处理器包括初始化为零的分支计数器，并且每当处理器解码除了呼叫分支指令之外的链接寄存器操作指令时，该分支计数器被设置为零。每当一个呼叫转移指令被解码并且一个地址被推到链路寄存器堆栈上时，分支计数器递增1。响应于解码返回分支指令并且提供的分支计数器不为零，解码的返回分支指令的目标地址从链接寄存器堆栈中弹出，分支计数器递减，并且不需要检查目标地址为正确。

97. 发明申请

US20140258692A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20140258692A1
公开(公告)日：2014-09-11
申请号：US14284342
申请日：2014-05-21
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Fumio ARAKAWA
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/3001 , G06F9/30029 , G06F9/30058 , G06F9/30094 , G06F9/3016 , G06F9/30181 , G06F9/3865
摘要： A RISC data processor in which the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. An instruction for generating flags according to operands' data sizes is defined, and an instruction set handled by the RISC data processor includes an instruction capable of executing an operation on operands in more than one data size. An identical operation process is conducted on the small-size operand and on low-order bits of the large-size operand, and flags are generated capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation. Thus, a reduction in instruction code space of the RISC data processor can be achieved.
摘要翻译：一个RISC数据处理器，其中由每个指令产生的标志数量增加，使得标志产生指令的减少超过了使用量的指令的增加，从而实现了指令的减少。定义用于根据操作数的数据大小生成标志的指令，并且由RISC数据处理器处理的指令集包括能够对多于一个数据大小的操作数执行操作的指令。对大尺寸操作数的小尺寸操作数和低位进行相同的操作处理，并且生成能够应对各个数据大小的标志，而与经受操作的每个操作数的数据大小无关。因此，可以实现RISC数据处理器的指令代码空间的减少。

98. 发明授权

US08806183B1 Blank bit and processor instructions employing the blank bit 有权
标题翻译：使用空白位的空白位和处理器指令
公开(公告)号：US08806183B1
公开(公告)日：2014-08-12
申请号：US11345803
申请日：2006-02-01
申请人： Gyle D. Yearsley
发明人： Gyle D. Yearsley
IPC分类号： G06F9/32
CPC分类号： G06F9/3001 , G06F9/30007 , G06F9/30018 , G06F9/30021 , G06F9/30043 , G06F9/30058 , G06F9/30094
摘要： Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors perform. To speed performance of such a task, a novel “blank bit” is added to the flag register of a processor. When a first instruction (arithmetic, logic or load) is executed, the instruction operands are checked to see if any is a NULL character value. Information on the result of the check is stored in the blank bit. Execution of a second instruction uses the information stored in the blank bit to determine whether or not a second operation (for example, a jump) will be performed. By using the first and second instructions in a loop, the number of instructions executed to check for NULLs at the end of strings and arrays is reduced.
摘要翻译：将值读入寄存器，检查值是否为NULL，然后如果值为NULL，则跳出循环是处理器执行的常见任务。为了加快这种任务的性能，将一个新颖的“空白位”添加到处理器的标志寄存器。当执行第一条指令（算术，逻辑或负载）时，将检查指令操作数，看看是否有NULL字符值。有关检查结果的信息存储在空白位。执行第二指令使用存储在空白位中的信息来确定是否将执行第二操作（例如，跳转）。通过在循环中使用第一个和第二个指令，减少了在字符串和数组结尾处执行以检查NULL的指令数量。

99. 发明申请

US20140173262A1 Energy-Focused Compiler-Assisted Branch Prediction 有权
标题翻译：能量聚焦编译器辅助分支预测
公开(公告)号：US20140173262A1
公开(公告)日：2014-06-19
申请号：US14097879
申请日：2013-12-05
申请人： BlueRISC Inc.
发明人： Saurabh Chheda , Kristopher Carver , Raksit Ashok
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058 , G06F9/3846 , G06F9/3848
摘要： A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.
摘要翻译：一种处理系统，用于降低处理器的能耗并提高编译器在选定分支指令之前插入的信息的性能，以静态暴露和控制预测应如何完成以及应采用哪种机制来实现能源和性能效率。

100. 发明申请

US20140173261A1 COMPUTER PROCESSOR WITH INSTRUCTION FOR EXECUTION BASED ON AVAILABLE INSTRUCTION SETS 有权
公开(公告)号：US20140173261A1
公开(公告)日：2014-06-19
申请号：US14100058
申请日：2013-12-09
申请人： International Business Machines Corporation
发明人： Jose E. Garza , Stephen J. Hobson
IPC分类号： G06F9/30
CPC分类号： G06F9/38 , G06F9/30058 , G06F9/466 , G06F11/1474 , G06F11/2236
摘要： A system and method for testing whether a computer processor is capable of executing a requested instruction set. The system includes a computer processor configured to receive an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implement the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor. The Method for testing whether a computer processor is capable of executing a requested instruction set, the method including, receiving an encoded conditional branch instruction in a form of machine code executable directly by the computer processor, and implementing the encoded conditional branch instruction unconditionally, based on underlying hardware architecture of the computer processor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式