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91. 发明授权

US5661674A Divide to integer 失效
标题翻译：划分为整数
公开(公告)号：US5661674A
公开(公告)日：1997-08-26
申请号：US472963
申请日：1995-06-07
申请人： Ronald Morton Smith, Sr.
发明人： Ronald Morton Smith, Sr.
IPC分类号： G06F7/499 , G06F7/52 , G06F7/535 , G06F7/38
CPC分类号： G06F7/535 , G06F7/4873 , G06F7/49957 , G06F7/49978
摘要： A system and method for providing an interruptible remainder instruction that can produce a quotient as well as a remainder. Remainders are computed through an iterative procedure. This procedure is carried out in a computer system's hardware by following a series of steps, the series being interruptible at any point. Each step reduces the magnitude of the dividend until the final remainder can be obtained. In the intermediate steps, the sign of the new (smaller in magnitude) dividend is kept the same as the sign of the original dividend, and the value Ni (which can be considered part of the quotient) is rounded toward zero. Only in the last step must the sign of the operands be considered and directed rounding be performed. Throughout the remainder operation, the partial quotients can be saved so that upon completion, not only has the remainder been computed, but so has the quotient.
摘要翻译：一种用于提供可产生商以及余数的可中断余数指令的系统和方法。剩余值通过迭代过程计算。该过程通过以下一系列步骤在计算机系统的硬件中进行，该系列在任何时候都是可中断的。每个步骤减少分红的幅度，直到可以获得最后的余数。在中间步骤中，新（较小幅度）的股息的符号与原始股利的符号保持一致，并且值Ni（可以被认为是商的一部分）被舍入为零。只有在最后一步必须考虑操作数的符号并执行四舍五入。在剩余操作中，可以保存部分商，以便在完成后，不仅计算余数，而且商数也是如此。

92. 发明授权

US5617346A Multiplication device using semiconductor memory 失效
标题翻译：使用半导体存储器的乘法器件
公开(公告)号：US5617346A
公开(公告)日：1997-04-01
申请号：US462901
申请日：1995-06-05
申请人： Genichiro Inoue
发明人： Genichiro Inoue
IPC分类号： G06F1/035 , G06F7/50 , G06F7/52
CPC分类号： G06F7/5324 , G06F1/0356 , G06F7/485 , G06F7/4876 , G06F7/535 , G06F7/49957
摘要： The present invention discloses a multiplication device. A multiplicand X of eight bits and a multiplier Y of eight bits are input and a product P of sixteen bits is found from these multiplication factors. MULTIPLICAND X is divided into two parts, an upper-order part X.sub.U of four bits and a low-order part X.sub.L of four bits. MULTIPLIER Y is likewise divided into two parts, an upper-order part Y.sub.U of four bits and a low-order part Y.sub.L of four bits. Thereafter, four 8-bit partial products, i.e., X.sub.L .times.Y.sub.L, X.sub.L .times.Y.sub.U, X.sub.U .times.Y.sub.L, and X.sub.U .times.Y.sub.U are computed one after another. These partial products are subjected to a digit place alignment addition operation, by an adder, to compute PRODUCT P. Computation of each of the partial products is implemented by performing addition of an approximate partial product AP retrieved by a 6-bit address from a 64-byte ROM, and a correction value H and a carry C generated by a correction value generator.
摘要翻译：本发明公开了一种乘法装置。输入8位的乘法器X和8位的乘法器Y，并从这些乘法因子中找到16位乘积P. MULTIPLICAND X被分为两部分，四位的高阶部分XU和四位的低阶部分XL。乘法器Y同样分为两部分，四位的高阶部分YU和四位的低阶部分YL。此后，一个接一个地计算四个8位部分乘积，即XLxYL，XLxYU，XUxYL和XUxYU。通过加法器对这些部分乘积进行数字位置对准加法运算，以计算出产品P P。通过执行由64位的6位地址检索的近似部分乘积AP的加法来实现每个部分乘积的计算字节ROM，以及由校正值发生器产生的校正值H和进位C。

93. 发明授权

US5587708A Division technique unified quantizer-dequantizer 失效
标题翻译：分割技术统一量化器 - 去量化器
公开(公告)号：US5587708A
公开(公告)日：1996-12-24
申请号：US184368
申请日：1994-01-19
申请人： Chung-Yen Chiu
发明人： Chung-Yen Chiu
IPC分类号： G06F7/52 , G06F7/72 , G06T9/00 , H04N7/26 , H04N7/50 , H03M2/36
CPC分类号： G06F7/535 , G06F7/72 , H04N19/126 , H04N19/61 , H04N19/124
摘要： A division technique unified quantizer-dequantizer circuit is disclosed. The unified quantizer-dequantizer includes a division circuit receiving a half step size q and an input signal x. The division circuit outputs a quantized coefficient signal y and a remainder R, where ##EQU1## The unified quantizer-dequantizer also includes a circuit receiving the quantized coefficient signal y, the remainder R, the half step size q and the input signal x. This circuit outputs a reconstructed signal r where, ##EQU2##
摘要翻译：公开了一种分割技术统一量化器 - 去量化器电路。统一的量化器 - 去量化器包括接收半步长q的分割电路和输入信号x。分频电路输出量化系数信号y和余数R，其中统一量化器反量化器还包括接收量化系数信号y的电路，余数R，半步长q和输入信号x。该电路输出重构信号r，其中

94. 发明授权

US5539684A Method and apparatus for calculating floating point exponent values 失效
标题翻译：用于计算浮点指数值的方法和装置
公开(公告)号：US5539684A
公开(公告)日：1996-07-23
申请号：US529469
申请日：1995-09-18
申请人： Eric E. Quintana , Daniel T. Marquette
发明人： Eric E. Quintana , Daniel T. Marquette
IPC分类号： G06F5/01 , G06F7/52 , G06F7/535 , G06F7/552
CPC分类号： G06F7/535 , G06F5/012 , G06F7/5525 , G06F7/4873
摘要： A data processing system (10) has a circuit for determining floating point exponents for divide operations and square root operations. The circuit has two input multiplexers (26 and 28) which provide exponent information or constants to an adder (30). The exponent information and constants are processed by the adder (30) to output three possible exponent values for either a divide operation or a square root operation. The three possible exponent values are stored in three registers (34, 36, and 38). A multiplexer (40) used mantissa rounding and normalizing information to determine which exponent of the three possible exponent values are correct for the current floating point calculation.
摘要翻译：数据处理系统（10）具有用于确定用于除法运算和平方根操作的浮点指数的电路。该电路具有向加法器（30）提供指数信息或常数的两个输入多路复用器（26和28）。加法器（30）处理指数信息和常数，以输出除法运算或平方根运算的三个可能的指数值。三个可能的指数值存储在三个寄存器（34,36和38）中。多路复用器（40）使用尾数舍入和归一化信息来确定三个可能指数值的指数对于当前浮点计算是否正确。

95. 发明授权

US5539682A Seed generation technique for iterative, convergent digital computations 失效
标题翻译：用于迭代，收敛数字计算的种子生成技术
公开(公告)号：US5539682A
公开(公告)日：1996-07-23
申请号：US175497
申请日：1993-12-30
申请人： Himanshu Jain , Charles C. Stearns
发明人： Himanshu Jain , Charles C. Stearns
IPC分类号： G06F1/035 , G06F7/52 , G06F7/535 , G06F7/552 , G06F7/00 , G06F7/38
CPC分类号： G06F7/535 , G06F1/035 , G06F7/5525 , G06F2101/08 , G06F2101/12 , G06F2207/5355 , G06F7/4873
摘要： A novel technique for improving the accuracy of seed values for iterative convergent computations such as square-root taking and division by providing optional dynamic range expansion as a part of the seed selection process is described. The technique, by improving seed accuracy, reduces the number of iterations required for convergence. This is accomplished with less hardware than would be required to accomplish the same result with a large ROM.
摘要翻译：描述了通过提供可选的动态范围扩展作为种子选择过程的一部分来提高用于迭代收敛计算的种子值的准确性的新技术，例如平方根获取和除法。该技术通过提高种子准确度，减少了收敛所需的迭代次数。这是通过使用较少的硬件来实现的，而不是用大的ROM来完成相同的结果所需要的硬件。

96. 发明授权

US5537345A Mathematical function processor utilizing table information 失效
标题翻译：数学函数处理器利用表信息
公开(公告)号：US5537345A
公开(公告)日：1996-07-16
申请号：US322537
申请日：1994-10-13
申请人： Hiraku Nakano
发明人： Hiraku Nakano
IPC分类号： G06F1/035 , G06F7/52 , G06F7/535 , G06F7/552 , G06F7/38
CPC分类号： G06F7/535 , G06F1/035 , G06F7/5525 , G06F2101/08 , G06F2101/12 , G06F2207/5521 , G06F7/4873
摘要： An input register holds, as an input operand to be square rooted, a floating-point number with an exponential radix is 2. An approximation of the reciprocal of a square root is retrieved from a table information store unit by an address composed of a least significant bit of an exponent and upper bits of a mantissa provided from the input register. The mantissa, with a leading bit appended, is normalized by a normalization circuit in units of two bits. An output of a remainder hold circuit in which a 0th remainder serves as a normalized operand is multiplied by a retrieved approximation to find a partial square root. Partial square roots found in iterative calculations are merged by a digit place alignment circuit and an adder. By making use of an inverter, a multiplicand generator, and an (R+S.times.T) arithmetic unit, a remainder being used in the next iterative calculation is found by subtracting a product of the merged square root times the partial square root from a remainder found in the preceding iterative calculation.
摘要翻译：输入寄存器保持作为平方根的输入操作数，具有指数基数的浮点数为2.平方根的倒数的近似从表信息存储单元通过由最少组成的地址来检索从输入寄存器提供的指数的有效位和尾数的高位。带有前导位的尾数由归一化电路以两位为单位进行归一化。将第0个余数作为归一化操作数的余数保持电路的输出乘以检索到的近似值以找到部分平方根。在迭代计算中发现的部分平方根由位置对齐电路和加法器合并。通过使用逆变器，被乘数发生器和（R + S×T）运算单元，在下一次迭代计算中使用的余数是通过从发现的余数中减去合并的平方根的乘积乘以部分平方根在前面的迭代计算中。

97. 发明授权

US5524091A Accurate digital divider 失效
标题翻译：精确的数字分频器
公开(公告)号：US5524091A
公开(公告)日：1996-06-04
申请号：US263439
申请日：1994-06-21
申请人： Robert Billing
发明人： Robert Billing
IPC分类号： G06F7/499 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/5354 , G06F2207/5356 , G06F7/49973
摘要： A digital divider for forming the quotient (Q) of two numbers (A,B) includes means providing values (Q+1, Q-1) of the quotient with possible rounding errors added to or subtracted therefrom. Selector switching means is arranged to select one of the values (Q, Q+1, Q-1) under the control of a logic circuit operating according to the following rules: ##EQU1##
摘要翻译：用于形成两个数字（A，B）的商（Q）的数字分频器包括提供商的值（Q + 1，Q-1）的装置，其中加上或从中减去可能的舍入误差。选择器切换装置被布置为在根据以下规则操作的逻辑电路的控制下选择一个值（Q，Q + 1，Q-1）：A> = 0且A> =（Q + 1）* B使用Q + 1 A> = 0，A <（Q + 1）* B使用QA <0，A> = Q * B使用QA <0，A

98. 发明授权

US5517439A Arithmetic unit for executing division 失效
标题翻译：用于执行分割的算术单元
公开(公告)号：US5517439A
公开(公告)日：1996-05-14
申请号：US382576
申请日：1995-02-02
申请人： Hidetoshi Suzuki , Toshihiro Ishikawa , Yukihiro Fujimoto , Noriaki Minamida
发明人： Hidetoshi Suzuki , Toshihiro Ishikawa , Yukihiro Fujimoto , Noriaki Minamida
IPC分类号： G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F2207/5352
摘要： An arithmetic unit includes an arithmetic and logic circuit having n bits and capable of controlling the execution of either addition or subtraction by responding to a signal indicative of a positive or negative sign of a result of one preceding calculation, a register of n bits for temporarily storing data delivered out of the arithmetic and logic circuit, a register of n bits for delivering a divisor to the arithmetic and logic circuit, a shift register of n stages for sequentially storing signals indicative of a positive or negative sign of results of calculation by the arithmetic and logic circuit, and a shifter for shifting data of the register by one bit to the left and inserting data of the most significant bit of the shift register into the least significant bit to provide an output which in turn is delivered to the arithmetic and logic circuit. A conventional shifter having a bit length of 2n can be replaced with the shifter having a bit length of n and the shift register having a bit length of n.
摘要翻译：算术单元包括具有n位的算术和逻辑电路，并且能够通过响应指示前一个计算的结果的正或负符号的信号来控制加法或减法的执行，暂时的n位寄存器存储从算术和逻辑电路传送的数据，将n个比特的寄存器传送到算术和逻辑电路; n个阶段的移位寄存器，用于顺序地存储指示计算结果的正或负符号的信号，算术和逻辑电路，以及用于将寄存器的数据向左移一位移位器，并将移位寄存器的最高有效位的数据插入到最低有效位中，以提供一个输出，该输出又被传递到算术和逻辑电路。具有2n长度的常规移位器可以用位长度为n的移位器和位长度为n的移位寄存器代替。

99. 发明授权

US5444647A Multiplier circuit and division circuit with a round-off function 失效
标题翻译：具有四舍五入功能的乘法器电路和除法电路
公开(公告)号：US5444647A
公开(公告)日：1995-08-22
申请号：US212926
申请日：1994-03-15
申请人： Michio Komoda
发明人： Michio Komoda
IPC分类号： G06F7/38 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/53 , G06F7/533
CPC分类号： G06F7/5312 , G06F7/535 , G06F7/49963 , G06F7/5338
摘要： A multiplier circuit has a smaller circuit size and operates at a higher speed. An addition processing part (31b) to which a partial product group 6 is inputted includes at its first stage half adders (7a) and (7c) and a rounding half adder (13). The addition processing part (31b) further includes full adders (8a), (8b) and (8c) at its second stage, full adders (8d), (8e) and (8f) at its third stage, and a 3-bit carry look ahead adder (9) at its fourth stage. A value outputted from the rounding half adder 13 is a sum of two inputs given thereto and a value 1. A rounding circuit for calculating a round number is therefore not necessary.
摘要翻译：乘法电路具有较小的电路尺寸并以更高的速度工作。输入部分乘积组6的加法处理部分（31b）包括第一级半加法器（7a）和（7c）和舍入半加法器（13）。加法处理部分（31b）在其第二级进一步包括全加法器（8a），（8b）和（8c），在其第三级具有全加器（8d），（8e）和（8f），以及3位在第四阶段携带前视加法器（9）。从舍入半加法器13输出的值是给出的两个输入和值1的和。因此，不需要用于计算循环数的舍入电路。

100. 发明授权

US5434809A Method and apparatus for performing floating point arithmetic operation and rounding the result thereof 失效
标题翻译：用于进行浮点算术运算并舍入其结果的方法和装置
公开(公告)号：US5434809A
公开(公告)日：1995-07-18
申请号：US219560
申请日：1994-03-29
申请人： Takashi Taniguchi
发明人： Takashi Taniguchi
IPC分类号： G06F7/02 , G06F7/483 , G06F7/499 , G06F7/52 , G06F7/53 , G06F7/533 , G06F7/535 , G06F7/544 , G06F7/552 , G06F17/17 , G06F7/38
CPC分类号： G06F7/535 , G06F7/026 , G06F7/544 , G06F7/5525 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49952 , G06F7/49957
摘要： An approximate square root Ya of a given value X is derived by referring to a relation Y=X.sup.1/2 at an accuracy at which an error between the approximate square root Ya and an infinitely precise square root Y is smaller than a weight of a digit in a digit place which is lower by two digit places than a least significant digit place for a final square root. The approximate square root Ya is rounded to an interim square root Yr equal to one of possible interim square roots which is closest to the approximate square root Ya. A value Xr is derived from the interim square root Yr using a relation Xr=Yr2. A sticky digit S is set to 0, 1, or -1 in response to a relation between the values X and Xr. The sticky digit S is added to a digit place having an order immediately lower than a lowest order digit place of the interim square root Yr, and a result of the addition is rounded in a designated rounding mode to obtain the final square root.
摘要翻译：通过参照关系Y = X1 / 2，以近似平方根Ya和无限精确平方根Y之间的误差小于数字的权重的精度来导出给定值X的近似平方根Ya 在比最终平方根的最低有效数字位数低两位数字的数字位置。近似平方根Ya被舍入为等于最接近近似平方根Ya的可能临时平方根之一的临时平方根Yr。使用关系Xr = Yr2从中间平方根Yr导出值Xr。响应于值X和Xr之间的关系，粘性数字S被设置为0,1或者-1。粘性数字S被添加到具有立即低于临时平方根Yr的最低位数位置的顺序的数字位置，并且以指定的舍入模式舍入结果，以获得最终的平方根。

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