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91. 发明申请

US20160267009A1 METHOD AND APPARATUS FOR MEMORY ALIASING DETECTION IN AN OUT-OF-ORDER INSTRUCTION EXECUTION PLATFORM 有权
标题翻译：用于外部指令执行平台内存存储器检测的方法和装置
公开(公告)号：US20160267009A1
公开(公告)日：2016-09-15
申请号：US14643354
申请日：2015-03-10
申请人： Oleg Margulis , Sumit Ahuja , Polychronis Xekalakis , Yongjun Park , Vineeth Mekkat , Igor Yanover , Sebastian Winkel , Ethan Schuchman
发明人： Oleg Margulis , Sumit Ahuja , Polychronis Xekalakis , Yongjun Park , Vineeth Mekkat , Igor Yanover , Sebastian Winkel , Ethan Schuchman
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/38 , G06F9/3834 , G06F9/3838 , G06F9/3855 , G06F9/467 , G06F2212/1008 , G06F2212/452
摘要： A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.
摘要翻译：描述了用于别名检测的处理器和方法。例如，设备的一个实施例包括：重新排序逻辑以按照程序顺序接收一组读取和写入操作，并响应于重新排序读取和写入操作; 调整信息附加逻辑，用于将调整信息与所述一组读取和写入操作中的一个或多个相关联，其中对于读取操作，所述调整信息用于指示所述读取操作已绕过的写入操作的数量，并且对于写入操作，所述调整信息是指示绕过了写入操作的多个读取操作; 以及无序处理逻辑，以确定重新排序的读取和写入操作的执行是否将导致至少部分地基于与所述一个或多个读取和写入相关联的调整信息的冲突。

92. 发明申请

US20160239414A1 PARALLEL GARBAGE COLLECTION IMPLEMENTED IN HARDWARE 有权
公开(公告)号：US20160239414A1
公开(公告)日：2016-08-18
申请号：US15141318
申请日：2016-04-28
申请人： International Business Machines Corporation
发明人： David F. Bacon , Perry S. Cheng , Sunil K. Shukla
IPC分类号： G06F12/02
CPC分类号： G06F12/0261 , G06F9/52 , G06F12/023 , G06F12/0238 , G06F12/0253 , G06F12/0269 , G06F12/121 , G06F2212/1008 , G06F2212/1016 , G06F2212/1044 , G06F2212/702 , Y02D10/13
摘要： Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing objects in a plurality of heaps, and operating a hardware garbage collector to free heap space. The hardware garbage collector traverses the heaps and marks selected objects, uses the marks to identify a plurality of the objects, and frees the identified objects. In an embodiment, the method comprises storing objects in a heap, each of at least some of the objects including a multitude of pointers; and operating a hardware garbage collector to free heap space. The hardware garbage collector traverses the heap, using the pointers of some of the objects to identify others of the objects; processes the objects to mark selected objects; and uses the marks to identify a group of the objects, and frees the identified objects.

93. 发明授权

US09411730B1 Private memory table for reduced memory coherence traffic 有权
公开(公告)号：US09411730B1
公开(公告)日：2016-08-09
申请号：US14745609
申请日：2015-06-22
申请人： International Business Machines Corporation
发明人： David M. Daly , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0815 , G06F3/06 , G06F12/0817 , G06F12/0831 , G06F12/084 , G06F2212/1008 , G06F2212/1016 , G06F2212/1021 , G06F2212/1048 , G06F2212/151 , G06F2212/251 , G06F2212/283 , G06F2212/608 , G06F2212/621
摘要： A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.

94. 发明授权

US09384141B2 Multi-core fuse decompression mechanism 有权
标题翻译：多芯保险丝减压机构
公开(公告)号：US09384141B2
公开(公告)日：2016-07-05
申请号：US14635026
申请日：2015-03-02
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： G. Glenn Henry , Dinesh K. Jain
IPC分类号： G06F13/12 , G11C17/18 , G11C7/00 , G11C8/00 , G06F12/08 , G11C17/16 , G06F3/06 , G06F9/44 , G06F9/445 , G06F12/06 , G11C29/00 , G06F11/10
CPC分类号： G06F12/0875 , G06F1/24 , G06F3/0604 , G06F3/0619 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4403 , G06F9/4405 , G06F9/44505 , G06F11/1008 , G06F11/1068 , G06F12/0646 , G06F12/0692 , G06F12/0802 , G06F12/0806 , G06F12/0811 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1012 , G06F2212/1032 , G06F2212/283 , G06F2212/452 , G06F2212/453 , G06F2212/601 , G06F2212/62 , G06F2212/69 , G11C17/16 , G11C17/18 , G11C29/52 , G11C29/802
摘要： An apparatus is contemplated for storing and decompressing configuration data in a multi-core microprocessor. The apparatus includes a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die and comprises a plurality of semiconductor fuses programmed with compressed configuration data. The plurality of microprocessor cores is also disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores have a reset controller that is configured to decompress the all of the compressed configuration data, and to distribute decompressed configuration data to initialize the elements.
摘要翻译：设想用于在多核微处理器中存储和解压缩配置数据的装置。该装置包括共享熔丝阵列和多个微处理器核。共享保险丝阵列设置在管芯上并且包括用压缩配置数据编程的多个半导体保险丝。多个微处理器核心也设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化内部的元件多个核心中的每一个。多个核心中的每一个具有复位控制器，其被配置为解压缩所有压缩的配置数据，并且分发解压缩的配置数据以初始化元件。

95. 发明授权

US09378033B2 Method and apparatus for a virtual system on chip 有权
标题翻译：虚拟系统芯片的方法和装置
公开(公告)号：US09378033B2
公开(公告)日：2016-06-28
申请号：US14452873
申请日：2014-08-06
申请人： Cavium, Inc.
发明人： Muhammad Raghib Hussain , Rajan Goyal , Richard Kessler
IPC分类号： G06F9/455 , G06F9/50 , G06F12/06 , G06F12/14
CPC分类号： G06F3/0622 , G06F3/0637 , G06F3/0644 , G06F3/0664 , G06F3/0683 , G06F9/455 , G06F9/45558 , G06F9/5077 , G06F12/0653 , G06F12/084 , G06F12/0897 , G06F12/14 , G06F12/1458 , G06F2009/45583 , G06F2212/1008 , G06F2212/152 , G06F2212/62
摘要： A virtual system on chip (VSoC) is an implementation of a machine that allows for sharing of underlying physical machine resources between different virtual systems. A method or corresponding apparatus of the present invention relates to a device that includes a plurality of virtual systems on chip and a configuring unit. The configuring unit is arranged to configure resources on the device for the plurality of virtual systems on chip as a function of an identification tag assigned to each virtual system on chip.
摘要翻译：虚拟片上系统（VSoC）是允许在不同虚拟系统之间共享底层物理机器资源的机器的实现。本发明的方法或对应的装置涉及一种包括多个芯片上的虚拟系统和配置单元的设备。配置单元被配置为根据分配给芯片上的每个虚拟系统的识别标签来配置芯片上的多个虚拟系统的设备上的资源。

96. 发明申请

US20160092367A1 HARDWARE APPARATUSES AND METHODS TO CONTROL ACCESS TO A MULTIPLE BANK DATA CACHE 有权
标题翻译：硬件设备和控制访问多个银行数据缓存的方法
公开(公告)号：US20160092367A1
公开(公告)日：2016-03-31
申请号：US14498902
申请日：2014-09-26
申请人： INTEL CORPORATION
发明人： Andrey Kluchnikov , Jayesh Iyer , Sergey Y. Shishlov , Boris A. Babayan
IPC分类号： G06F12/08
CPC分类号： G06F12/0844 , G06F3/0613 , G06F3/0637 , G06F3/0659 , G06F3/0673 , G06F9/52 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F13/18 , G06F2212/1008 , G06F2212/1016 , G06F2212/251 , G06F2212/452
摘要： Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
摘要翻译：描述了控制对多存储体数据缓存的访问的方法和装置。在一个实施例中，处理器包括冲突解决逻辑，以检测被调度以在相同时钟周期内访问多存储体数据高速缓存的相同存储体的多个指令，并且为预定访问最高总数的多个指令的指令授予访问优先级银行多银行数据缓存。在另一个实施例中，一种方法包括检测被调度以在相同时钟周期内访问多存储体数据高速缓存的同一个存储体的多个指令，以及授予被调度以访问该多个存储体中多个存储体的最高总数组的多个指令的指令的访问优先级银行数据缓存。

97. 发明申请

US20160092123A1 MEMORY WRITE MANAGEMENT IN A COMPUTER SYSTEM 审中-公开
标题翻译：计算机系统中的存储器写入管理
公开(公告)号：US20160092123A1
公开(公告)日：2016-03-31
申请号：US14499063
申请日：2014-09-26
申请人： Pankaj KUMAR , Samantha J. EDIRISOORIYA , Roger C. JEPPSEN
发明人： Pankaj KUMAR , Samantha J. EDIRISOORIYA , Roger C. JEPPSEN
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F13/1652 , G06F2212/1008 , H04L67/025 , H04L67/04 , H04L67/1097
摘要： In accordance with the present description, an apparatus for use with a source issuing write operations to a target, wherein the device includes an I/O port, and logic of the target configured to detect a flag issued by the source in association with the issuance of a first plurality of write operations. In response to detection of the flag, the logic of the target ensures that the first plurality of write operations are completed in a memory prior to completion of any of the write operations of the second plurality of write operations. Other aspects are described herein.
摘要翻译：根据本说明书，一种用于向目标发出写入操作的源的装置，其中所述设备包括I / O端口，并且所述目标的逻辑被配置为检测由所述源发布的与发布相关联的标志的第一多个写入操作。响应于标志的检测，目标的逻辑确保在完成第二多个写入操作的任何写入操作之前在存储器中完成第一多个写入操作。本文描述了其它方面。

98. 发明申请

US20160085688A1 Multi-Source Address Translation Service (ATS) With A Single ATS Resource 有权
标题翻译：具有单一ATS资源的多源地址转换服务（ATS）
公开(公告)号：US20160085688A1
公开(公告)日：2016-03-24
申请号：US14493417
申请日：2014-09-23
申请人： Itay Franko
发明人： Itay Franko
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/10 , G06F12/0802 , G06F12/0864 , G06F12/1081 , G06F13/28 , G06F2212/1008 , G06F2212/60 , G06F2212/6032 , G06F2212/608 , G06F2212/65 , G06F2212/651
摘要： Disclosed is an address translation system. The apparatus includes a memory management unit (MMU) that is operable to receive a translation request for an original address and translate the original address to a translated address as a second-level address translation service (ATS). The apparatus also includes an address translator having an associated cache to store the original address and the first translated address. The address translator is to translate memory addresses as a first-level address translation service (ATS). The address translator determines whether the transaction is to be processed using either the first-level ATS or the second-level ATS. The address translator translates a current memory address of the transaction to a current translated address using the first-level ATS or the second-level ATS based on the determination, The address translator also dispatches the transaction with the current translated address to a memory device where it may be further processed.
摘要翻译：公开了一种地址翻译系统。该装置包括存储器管理单元（MMU），其可操作以接收原始地址的翻译请求，并将原始地址转换为作为二级地址转换服务（ATS）的翻译地址。该设备还包括具有相关联的高速缓存以存储原始地址和第一翻译地址的地址转换器。地址转换器将内存地址翻译为第一级地址转换服务（ATS）。地址转换器确定是使用第一级ATS还是第二级ATS来处理事务。地址转换器基于确定，使用第一级ATS或第二级ATS将事务的当前存储器地址转换为当前转换的地址。地址转换器还将具有当前转换的地址的事务分派到存储器件，其中可以进一步处理。

99. 发明申请

US20160004468A1 DATA-STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD 有权
标题翻译：数据存储设备和闪速存储器控制方法
公开(公告)号：US20160004468A1
公开(公告)日：2016-01-07
申请号：US14851186
申请日：2015-09-11
申请人： Silicon Motion, Inc.
发明人： Chang-Kai CHENG
IPC分类号： G06F3/06 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F12/1009 , G06F2212/1008 , G06F2212/152 , G06F2212/2022 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207
摘要： A data-storage device having a flash memory allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information, and an invalid block record. The data-storage device further having a controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to manage the data-storage space. A FLASH memory control method is also provided.
摘要翻译：具有分配用于提供数据存储空间的闪速存储器，有效页计数表，逻辑到物理地址映射信息和无效块记录的数据存储设备。数据存储装置还具有控制器，分配数据存储空间以存储从主机发出的数据，以及建立和维护有效页计数表，逻辑到物理地址映射信息和无效块记录 FLASH存储器来管理数据存储空间。还提供了一种闪速存储器控制方法。

100. 发明申请

US20150378907A1 DYNAMIC PREDICTOR FOR COALESCING MEMORY TRANSACTIONS 有权
公开(公告)号：US20150378907A1
公开(公告)日：2015-12-31
申请号：US14845403
申请日：2015-09-04
申请人： International Business Machines Corporation
发明人： Fadi Y. Busaba , Harold W. Cain, III , Michael Karl Gschwind , Maged M. Michael , Eric M. Schwarz
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F3/067 , G06F9/467 , G06F12/0831 , G06F12/084 , G06F2212/1008 , G06F2212/1016
摘要： A transactional memory system predicts the outcome of coalescing outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction, the method comprising. A processor of the transactional memory system determines whether a first plurality of outermost transactions from an associated program that were coalesced experienced an abort, the first plurality of outermost transactions including a first instance of a first transaction. The processor updates a history of the associated program to reflect the results of the determination. The processor coalesces a second plurality of outermost transactions from the associated program, based, at least in part, on the updated history.

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