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91. 发明申请

US20170024318A1 TRANSACTIONAL MEMORY OPERATIONS WITH WRITE-ONLY ATOMICITY 有权
标题翻译：具有写入原理的交易记忆操作
公开(公告)号：US20170024318A1
公开(公告)日：2017-01-26
申请号：US15287800
申请日：2016-10-07
申请人： International Business Machines Corporation
发明人： Michael Karl Gschwind , Chung-Lung K. Shum , Timothy J. Slegel
IPC分类号： G06F12/084 , G06F9/30 , G06F12/0875 , G06F12/0815 , G06F9/46
CPC分类号： G06F12/084 , G06F3/0619 , G06F3/0653 , G06F3/0674 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/467 , G06F12/0815 , G06F12/0833 , G06F12/0875 , G06F12/1027 , G06F2212/60 , G06F2212/621 , G06F2212/682
摘要： Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional execution. Write-set conflicts may still cause a transactional abort. Absent any aborting, the transaction's execution may complete, by committing transactional stores to memory and updating architecture states.
摘要翻译：事务模式设置指令的执行使得计算机处理器处于原子只写模式，在事务执行期间忽略与事务的某些读取集的冲突。写集冲突可能仍然导致事务中止。没有任何中止，交易的执行可能完成，通过提交交易存储到内存和更新架构状态。

92. 发明授权

US09542316B1 System and method for adaptation of coherence models between agents 有权
标题翻译：代理之间的相干模型的适应系统和方法
公开(公告)号：US09542316B1
公开(公告)日：2017-01-10
申请号：US14970467
申请日：2015-12-15
申请人： Arteris, Inc.
发明人： Craig Stephen Forrest , David A. Kruckemyer
IPC分类号： G06F12/00 , G06F12/08 , G06F13/00 , G06F13/28 , G06F9/30
CPC分类号： G06F12/0815 , G06F9/3017 , G06F12/0817 , G06F2212/621
摘要： A system and method are disclosed for multiple coherent caches supporting agents that use different, incompatible coherence models. Compatibility is implemented by translators that accept coherency requests and snoop responses from an agent and accept snoop requests and coherency responses from a coherence controller. The translators issue corresponding coherency requests and snoop responses to the coherence controller and issue corresponding coherency responses and snoop requests to the agent. Interaction between translators and the coherence controller accord with a generic coherence model, which may be a subset, superset, or partially inclusive of features of any native coherence model. A generic coherence protocol may include binary values for each of characteristics: valid or invalid, owned or non-owned, unique or shared, and clean or dirty.
摘要翻译：公开了一种使用不同的，不兼容的相干模型的多个相干缓存支持代理的系统和方法。兼容性由接受来自代理的一致性请求和窥探响应的翻译器实现，并接受来自一致性控制器的窥探请求和一致性响应。翻译者向相干控制器发出相应的一致性请求和窥探响应，并向代理发出相应的一致性响应和窥探请求。翻译者和相干控制器之间的相互作用符合通用相干模型，其可以是任何天生相干模型的子集，超集或部分包含特征。通用一致性协议可以包括每个特征的二进制值：有效或无效，拥有或非拥有，唯一或共享，干净或脏。

93. 发明申请

US20160378540A1 MULTITHREADED TRANSACTIONS 有权
标题翻译：多元化交易
公开(公告)号：US20160378540A1
公开(公告)日：2016-12-29
申请号：US14751979
申请日：2015-06-26
申请人： International Business Machines Corporation
发明人： Fadi Y. Busaba , Michael K. Gschwind , Valentina Salapura , Eric M. Schwarz , Chung-Lung K. Shum
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/467 , G06F3/0604 , G06F3/061 , G06F3/0637 , G06F3/0659 , G06F3/0673 , G06F9/4881 , G06F12/0811 , G06F12/0815 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F13/1663 , G06F2212/1016 , G06F2212/314 , G06F2212/6042 , G06F2212/621
摘要： Embodiments relate to multithreaded transactions. An aspect includes assigning a same transaction identifier (ID) corresponding to the multithreaded transaction to a plurality of threads of the multithreaded transaction, wherein the plurality of threads execute the multithreaded transaction in parallel. Another aspect includes determining one or more memory areas that are owned by the multithreaded transaction. Another aspect includes receiving a memory access request from a requester that is directed to a memory area that is owned by the transaction. Yet another aspect includes based on determining that the requester has a transaction ID that matches the transaction ID of the multithreaded transaction, performing the memory access request without aborting the multithreaded transaction.
摘要翻译：实施例涉及多线程事务。一个方面包括将与多线程事务相对应的相同事务标识符（ID）分配给多线程事务的多个线程，其中多个线程并行执行多线程事务。另一方面包括确定由多线程事务拥有的一个或多个存储器区域。另一方面包括从请求者接收指向由该事务拥有的存储区域的存储器访问请求。另一方面包括基于确定请求者具有与多线程事务的事务ID匹配的事务ID，执行存储器访问请求而不中止多线程事务。

94. 发明申请

US20160378382A1 ADDRESS PROBING FOR TRANSACTION 有权
标题翻译：地址查询交易
公开(公告)号：US20160378382A1
公开(公告)日：2016-12-29
申请号：US14751919
申请日：2015-06-26
申请人： International Business Machines Corporation
发明人： Fadi Y. Busaba , Harold W. Cain, III , Dan F. Greiner , Michael K. Gschwind , Maged M. Michael , Eric M. Schwarz , Valentina Salapura , Timothy J. Slegel
IPC分类号： G06F3/06 , G06F9/46
CPC分类号： G06F3/0622 , G06F3/0659 , G06F3/0673 , G06F9/466 , G06F9/467 , G06F9/52 , G06F12/0811 , G06F12/0815 , G06F12/084 , G06F12/0844 , G06F12/0862 , G06F12/1466 , G06F2212/6024 , G06F2212/621
摘要： Embodiments relate to address probing for a transaction. An aspect includes determining, before starting execution of a transaction, a plurality of addresses that will be used by the transaction during execution. Another aspect includes probing each address of the plurality of addresses to determine whether any of the plurality of addresses has an address conflict. Yet another aspect includes, based on determining that none of the plurality of addresses has an address conflict, starting execution of the transaction.
摘要翻译：实施例涉及交易的地址探测。一方面包括在开始执行事务之前确定将在执行期间由事务使用的多个地址。另一方面包括探测多个地址的每个地址以确定多个地址中的任何地址是否具有地址冲突。另一方面包括，基于确定多个地址中没有一个地址具有地址冲突，开始执行交易。

95. 发明授权

US09514083B1 Topology specific replicated bus unit addressing in a data processing system 有权
公开(公告)号：US09514083B1
公开(公告)日：2016-12-06
申请号：US14960507
申请日：2015-12-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Richard L. Arndt , Florian Auernhammer , Hugh Shen , Derek E. Williams
IPC分类号： G06F13/40 , G06F13/28 , G06F13/24 , G06F12/08 , G06F9/54 , G06F9/38 , G06F9/30
CPC分类号： G06F13/404 , G06F9/3004 , G06F9/30043 , G06F9/3891 , G06F9/544 , G06F12/0815 , G06F12/0875 , G06F12/0888 , G06F13/24 , G06F13/28 , G06F13/364 , G06F13/4282 , G06F2212/1056 , G06F2212/452
摘要： A technique for handling cache-inhibited operations in a data processing system includes receiving, at a replicated bus unit, a cache-inhibited (CI) operation. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit and whether a source indicated by the CI operation is associated with the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit and the source indicated by the CI operation being associated with the replicated bus unit, the replicated bus unit processes the CI operation. In response to the address associated with the CI operation not matching the address for the replicated bus unit or the source indicated by the CI operation not being associated with the replicated bus unit, the replicated bus unit ignores the CI operation.

96. 发明授权

US09514045B2 Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system 有权
标题翻译：在弱有序的记忆体系中实施有效支持累积性的障碍的技术
公开(公告)号：US09514045B2
公开(公告)日：2016-12-06
申请号：US14245156
申请日：2014-04-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F9/312 , G06F9/52 , G06F12/00 , G06F12/08 , G06F12/12 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30087 , G06F9/3836 , G06F9/3838 , G06F9/522 , G06F12/0815 , G06F12/0842 , G06F12/0897 , G06F12/128 , G06F2212/284 , G06F2212/6042
摘要： A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory. Dependencies in a dependency data structure of a store queue of the cache memory are set based on the pollution vectors to reduce unnecessary ordering effects. Store operations are dispatched from the store queue in accordance with the dependencies indicated by the dependency data structure.
摘要翻译：用于操作数据处理系统的高速缓冲存储器的技术包括创建相应的污染向量，以跟踪由相关联的处理器核心执行的多个并发线程当前被驻留在高速缓存存储器中的存储操作所污染的哪一个。基于污染向量设置缓存存储器的存储队列的依赖性数据结构中的依赖关系，以减少不必要的排序效应。存储操作根据依赖关系数据结构指示的依赖关系从存储队列中发出。

97. 发明授权

US09507732B1 System and method for cache management 有权
标题翻译：用于缓存管理的系统和方法
公开(公告)号：US09507732B1
公开(公告)日：2016-11-29
申请号：US13630746
申请日：2012-09-28
申请人： EMC Corporation
发明人： Assaf Natanzon , Philip Derbeko , Anat Eyal
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/12 , G06F3/06 , G06F9/50 , G06F11/1076 , G06F12/0806 , G06F12/0813 , G06F12/0815 , G06F12/0842 , G06F12/0862 , G06F12/0868 , G06F12/0897 , G06F2212/1016 , G06F2212/152 , G06F2212/222 , G06F2212/262 , G06F2212/282 , G06F2212/311 , G06F2212/313 , G06F2212/6024
摘要： A method, computer program product, and computing system for associating a tracking file with a multi-portion data file located on a data array. The tracking file is configured to monitor the status of each portion of the multi-portion data file. At least one portion of the multi-portion data file is modified via a virtual machine executed on a first physical machine. The tracking file is updated to reflect the modification of the at least one portion of the multi-portion data file.
摘要翻译：一种用于将跟踪文件与位于数据阵列上的多部分数据文件相关联的方法，计算机程序产品和计算系统。跟踪文件被配置为监视多部分数据文件的每个部分的状态。通过在第一物理机器上执行的虚拟机来修改多部分数据文件的至少一部分。跟踪文件被更新以反映多部分数据文件的至少一部分的修改。

98. 发明申请

US20160342524A1 PROCESSOR INCLUDING SINGLE INVALIDATE PAGE INSTRUCTION 有权
标题翻译：处理器包括单个无效页面指令
公开(公告)号：US20160342524A1
公开(公告)日：2016-11-24
申请号：US14718201
申请日：2015-05-21
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： COLIN EDDY
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/0815 , G06F12/0891 , G06F2212/621 , G06F2212/683
摘要： A processor including a translation lookaside buffer (TLB), an instruction translator, and a memory subsystem. The TLB caches virtual to physical address translations. The instruction translator incorporates a microinstruction set for the processor that includes a single invalidate page instruction. The invalidate page instruction, when executed by the processor, causes the processor to perform a pseudo translation process in which a virtual address is submitted to the TLB to identify matching entries in the TLB that match the virtual address. The memory subsystem invalidates the matching entries in the TLB. The TLB may include a data TLB and an instruction TLB. The memory subsystem may include a tablewalk engine that performs a pseudo tablewalk to invalidate entries in the TLB and in one or more paging caches. The invalidate page instruction may specify invalidation of only those entries indicated as local.
摘要翻译：包括翻译后备缓冲器（TLB），指令转换器和存储器子系统的处理器。 TLB将虚拟缓存缓存到物理地址转换。指令转换器包含一个包含单个无效页指令的处理器微指令集。无效页指令在由处理器执行时使处理器执行伪翻译处理，其中虚拟地址被提交给TLB以识别与虚拟地址匹配的TLB中的匹配条目。内存子系统使TLB中匹配的条目无效。 TLB可以包括数据TLB和指令TLB。存储器子系统可以包括执行伪行进以使TLB中的条目和一个或多个寻呼高速缓存中的条目无效的桌面引擎。无效页面指令可以指定仅指示为本地的条目的无效。

99. 发明授权

US09501409B2 Concurrent accesses of dynamically typed object data 有权
标题翻译：动态类型对象数据的并发访问
公开(公告)号：US09501409B2
公开(公告)日：2016-11-22
申请号：US14231464
申请日：2014-03-31
申请人： Apple Inc.
发明人： Filip J. Pizlo
IPC分类号： G06F9/44 , G06F12/08 , G06F9/455 , G06F9/45
CPC分类号： G06F12/0815 , G06F8/315 , G06F8/4443 , G06F9/4491 , G06F9/451 , G06F9/45504 , G06F9/45508 , G06F9/45516 , G06F9/4552 , G06F9/45529 , G06F2212/621
摘要： A method and an apparatus for an enhanced object model to allow concurrent execution for program code generated from dynamic programming languages, such as JavaScript, are described. An index structure may be introduced to an object model representing a dynamically typed object in addition to a type structure and a data payload storing property or field values of the object. Elements of the index structure may point at corresponding property values as an indirection for accessing the object.
摘要翻译：描述了用于允许从动态编程语言（例如JavaScript）生成的程序代码的并发执行的增强对象模型的方法和装置。索引结构可以被引入到表示动态类型对象的对象模型，除了类型结构和数据有效载荷存储对象的属性或字段值之外。索引结构的元素可以指向相应的属性值作为访问对象的间接。

100. 发明授权

US09495192B2 NUMA I/O aware network queue assignments 有权
标题翻译： NUMA I / O感知网络队列分配
公开(公告)号：US09495192B2
公开(公告)日：2016-11-15
申请号：US14530574
申请日：2014-10-31
申请人： VMWare, Inc.
发明人： Rishi Mehta , Xiaochuan Shen , Amitabha Banerjee , Ayyappan Veeraiyan
IPC分类号： G06F9/46 , G06F9/455 , G06F12/02 , G06F12/08 , G06F9/445
CPC分类号： G06F9/45558 , G06F9/50 , G06F12/0223 , G06F12/023 , G06F12/0815 , G06F2009/4557 , G06F2009/45583 , G06F2212/2542
摘要： Systems and methods for preferentially assigning virtual machines (VMs) on a particular NUMA node with network queues on the same NUMA node are described. A load balancer process on a host assigns multiple VMs to network queues. The assignment of the VMs to a network queues is performed with a bias toward assigning VMs using a particular NUMA node to network queues on the same NUMA node. A scheduler on the host assigns VMs to NUMA nodes. The scheduler is biased toward assigning VMs to the same NUMA node as the PNIC and/or the same NUMA node as a network queue assigned to the VM.
摘要翻译：描述用于在具有相同NUMA节点上的网络队列的特定NUMA节点上优先分配虚拟机（VM）的系统和方法。主机上的负载均衡器进程将多个虚拟机分配给网络队列。将虚拟机分配给网络队列的方式是偏向于使用特定的NUMA节点将VM分配到同一NUMA节点上的网络队列。主机上的调度程序将VM分配给NUMA节点。调度器偏向于将VM分配给与作为分配给VM的网络队列的PNIC和/或相同的NUMA节点相同的NUMA节点。

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