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91. 发明授权

US06717429B2 IC having comparator inputs connected to core circuitry and output pad 有权
标题翻译： IC具有连接到核心电路和输出板的比较器输入
公开(公告)号：US06717429B2
公开(公告)日：2004-04-06
申请号：US09896467
申请日：2001-06-29
申请人： Lee D. Whetsel
发明人： Lee D. Whetsel
IPC分类号： G01R3102
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318566 , G01R31/318572 , G01R31/31926 , G01R31/31932 , G06F11/26 , G06F11/277
摘要： As IC circuit density increases, the testing of ICs becomes more complex and costly for the IC manufacturers. A test system and method achieves cost reduction in testing by permitting simultaneous testing of a plurality of semiconductor die. The testing can occur while the die are on a wafer or after the die have been packaged.
摘要翻译：随着IC电路密度的增加，IC制造商的IC测试变得更加复杂和昂贵。测试系统和方法通过允许多个半导体管芯的同时测试来实现测试成本降低。当芯片在晶片上或芯片封装后，可以进行测试。

92. 发明申请

US20030169061A1 Closed-grid bus architecture for wafer interconnect structure 有权
公开(公告)号：US20030169061A1
公开(公告)日：2003-09-11
申请号：US10406669
申请日：2003-04-02
申请人： FORMFACTOR, INC.
发明人： Charles A. Miller , John Matthew Long
IPC分类号： G01R031/02
CPC分类号： G01R31/31926 , G01R1/07378 , G01R31/318511 , G11C29/56 , G11C2029/2602 , H05K1/0216 , H05K1/023 , H05K1/0289 , H05K2201/09254 , Y10T29/49117
摘要： An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

93. 发明申请

US20030141890A1 Apparatus and method for the parallel and independent testing of voltage-supplied semiconductor devices 失效
标题翻译：用于并联和独立测试电压供应的半导体器件的装置和方法
公开(公告)号：US20030141890A1
公开(公告)日：2003-07-31
申请号：US10352729
申请日：2003-01-27
发明人： Udo Hartmann
IPC分类号： G01R031/26
CPC分类号： G01R31/318505 , G01R31/318511
摘要： An apparatus for the parallel and independent testing of a plurality of semiconductor devices disposed on a wafer, in which the semiconductor devices are in each case connected to a common voltage supply unit through a controllable isolating apparatus, a voltage-regulating unit, and a current-limiting unit, and to a method for operating such an apparatus.
摘要翻译：一种用于平行和独立测试设置在晶片上的半导体器件的装置，其中半导体器件在每种情况下都通过可控隔离装置连接到公共电压供应单元，电压调节单元和电流限制单元，以及用于操作这种装置的方法。

94. 发明申请

US20030075741A1 Method of manufacturing an integrated circuit, integrated circuit obtained in accordance with said method, wafer provided with an integrated circuit obtained in accordance with the method, and system comprising an integrated circuit obtained by means of the method 有权
标题翻译：制造集成电路的方法，根据所述方法获得的集成电路，提供有根据该方法获得的集成电路的晶片，以及包括通过该方法获得的集成电路的系统
公开(公告)号：US20030075741A1
公开(公告)日：2003-04-24
申请号：US10253235
申请日：2002-09-24
发明人： Anton Petrus Maria Van Arendonk , Edwin Roks , Adrianus Johannes Mierop
IPC分类号： H01L027/148
CPC分类号： G01R31/318505 , G01R31/318511 , G01R31/3187
摘要： The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode. The invention also relates to an integrated circuit (404) obtained by means of the manufacturing method, a wafer (401) comprising an integrated circuit (404) obtained by means of the manufacturing method, and a system comprising an integrated circuit (404) obtained by means of the manufacturing method.
摘要翻译：本发明涉及在芯片（402）上制造集成电路（404）的方法，其中模具（402）形成晶片（401）的可拆卸部分，该晶片包括通过切割相互分离的多个管芯车道（403）。该方法包括在至少一个切割通道（403）中施加金属化图案（407）以形成包括作为集成电路（404）的一部分的至少一个通信总线电路（405）的通信总线的步骤。所述步骤之后是其中根据使用通信总线电路（405）与集成电路（404）通信的预定测试方法测试集成电路（404）的步骤。该步骤之后是其中模具（402）与晶片（401）分离的下一步骤。通信总线电路（405）被设计成在晶片测试模式以及功能模式下进行通信。在集成电路（404）的测试期间，它以晶片测试模式进行通信。本发明还涉及通过制造方法获得的集成电路（404），包括通过制造方法获得的集成电路（404）的晶片（401）和包括获得的集成电路（404）的系统，通过制造方法。

95. 发明申请

US20030014704A1 Test apparatus for semiconductor devices having bult-in self-test function 审中-公开
标题翻译：具有嵌入式自检功能的半导体器件测试装置
公开(公告)号：US20030014704A1
公开(公告)日：2003-01-16
申请号：US10098442
申请日：2002-03-18
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Yasumasa Nishimura
IPC分类号： G01R031/28
CPC分类号： G01R31/318511 , G01R31/318505 , G01R31/3187
摘要： A test apparatus for semiconductor devices comprises a self-test circuit carried on the semiconductor device and for test the semiconductor device. A tester supplies data signals, clock signals, and expected value data to the self-test circuit. A comparing and judging circuit compares the result of test with the expected-value data to judge the quality of the semiconductor device. A non-volatile memory cell stores the results of judgment.
摘要翻译：一种用于半导体器件的测试装置包括在半导体器件上承载并用于测试半导体器件的自检电路。测试仪将数据信号，时钟信号和预期值数据提供给自检电路。比较判断电路将测试结果与预期值数据进行比较，以判断半导体器件的质量。非易失性存储单元存储判断结果。

96. 发明申请

US20030013249A1 Semiconductor wafer, semiconductor chip, semiconductor device and method for manufacturing semiconductor device 审中-公开
公开(公告)号：US20030013249A1
公开(公告)日：2003-01-16
申请号：US10244522
申请日：2002-09-17
申请人： Hitachi, Ltd.
发明人： Kazuki Honma , Terutaka Okada , Fumiaki Kitajima , Takahiro Hatazawa , Hiroyuki Motomatsu , Katsuhiro Haruyama
IPC分类号： H01L021/8238
CPC分类号： G01R31/318511 , G01R31/318505 , G11C11/41 , G11C16/04 , G11C29/006 , G11C2029/4402 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： There is provided an electrical characteristic test technique for a semiconductor device that can shorten the time required for a next probe test after a wafer level burn-in test, prevent leak of defective product to an assembling process and moreover easily realizes the analysis of cause for generation of a fault after delivery of products to customers. In this electrical characteristic test technique, a multi-chip package MCP mounts a couple of semiconductor chips of flash memory and SRAM, a simultaneous contact check is executed for an input/output pad of each semiconductor chip and an erase/write mode and a read mode are respectively executed for a memory array of each semiconductor chip depending on the steps S201 to S211 on the occasion of conducting the wafer level burn-in of the semiconductor chip of flash memory, historical data of these test results is written into the semiconductor chip of flash memory and the historical data written in the wafer level burn-in process is read in a next probe test process and the probe test is continuously implemented only to the semiconductor chip of a good product.

97. 发明申请

US20020173926A1 Method and system for wafer and device-level testing of an integrated circuit 失效
标题翻译：集成电路的晶圆和器件级测试方法和系统
公开(公告)号：US20020173926A1
公开(公告)日：2002-11-21
申请号：US09980509
申请日：2001-10-19
发明人： Don McCord
IPC分类号： G01R031/14
CPC分类号： G11C29/006 , G01R31/30 , G01R31/3016 , G01R31/318505 , G01R31/318511 , G01R31/31905 , G01R31/31924 , G01R31/31926 , G11C7/1066 , G11C29/48 , G11C29/56
摘要： A tester comprises test logic and a connector for at least one device under test. The connector, which may comprise a wafer probe for dice on a wafer or a test fixture for packaged integrated circuit devices, has connections for the device under test that present an impedance selected to emulate the characteristic impedance of an end-use environment of the device under test. For example, in an embodiment in which the device under test comprises Rambus memory and the end-use environment is a Rambus channel, the characteristic impedance is between approximately 20 and 60 ohms. If, on the other hand, the end-use environment is a Rambus memory module, then the characteristic impedance is approximately 28 ohms. Thus, the tester of the present invention can accurately simulate operational behavior in an end-use environment of the device under test. Because this accurate simulation is available even for dice on a wafer, the needless expense associated with packaging defective dies and assembling defective dies into modules can be avoided. The test logic, which is coupled to the connector for communication with the device under test, transfers test commands and test data to the device under test. The test data and commands are utilized to perform multiples types of tests, including tests of the core logic and interface logic of the device under test. In this manner, the need for multiple types of testers is reduced or eliminated.
摘要翻译：测试仪包括测试逻辑和用于至少一个被测设备的连接器。可以包括用于晶片上的晶片的晶片探针或用于封装的集成电路器件的测试夹具的连接器具有用于被测器件的连接，其提供被选择用于模拟器件的最终使用环境的特性阻抗的阻抗被测试。例如，在其中待测器件包括Rambus存储器并且最终使用环境是Rambus通道的实施例中，特征阻抗在大约20和60欧姆之间。另一方面，如果终端使用环境是Rambus存储器模块，则特性阻抗约为28欧姆。因此，本发明的测试器可以准确地模拟被测设备的最终使用环境中的操作行为。由于即使在晶片上的骰子也可以使用这种精确的模拟，因此可以避免与将包装有缺陷的模具和将有缺陷的模具组装成模块相关的不必要的费用。耦合到连接器的测试逻辑与被测器件通信，将测试命令和测试数据传送到被测器件。测试数据和命令用于执行多种测试类型，包括测试被测设备的核心逻辑和接口逻辑的测试。以这种方式，减少或消除了对多种类型的测试器的需要。

98. 发明申请

US20020072135A1 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20020072135A1
公开(公告)日：2002-06-13
申请号：US10006243
申请日：2001-12-10
发明人： Hiroyuki Adachi , Masayuki Sato
IPC分类号： H01L021/66 , G01R031/26
CPC分类号： G01R31/318505 , G01R31/318511
摘要： A manufacturing method of a semiconductor integrated circuit device includes the steps of: providing wiring conductors capable of connecting between chips or devices and variable switching devices capable of connecting between predetermined wiring conductors on a wafer formed of a microcomputer built-in chip having a CPU and a writable memory circuit for storing an operation program or on a testing board provided with a microcomputer built-in device enclosed by a package; writing a testing program including the transmission and reception operation of signals between the devices or chips into the memory circuit re-writable and capable of using as a program storing area for one of the chips or devices; and executing the testing program in the CPU of the chip or device, thereby testing a testing chip, between the device and the testing chip or an input/output circuit of the device.
摘要翻译：半导体集成电路器件的制造方法包括以下步骤：提供能够在芯片或器件之间连接的布线导体和能够连接在由具有CPU的微型计算机内置芯片形成的晶片上的预定布线导体之间的可变开关器件;以及用于存储操作程序的可写存储器电路或设置有由封装件包围的微计算机内置装置的测试板; 将包括在所述设备或芯片之间的信号的发送和接收操作的测试程序写入可重写的存储器电路并且能够用作所述芯片或设备之一的程序存储区域; 并在芯片或设备的CPU中执行测试程序，从而测试设备与测试芯片之间的测试芯片或器件的输入/输出电路。

99. 发明授权

US06388460B1 Alternate timing wafer burn-in method 有权
标题翻译：替代定时晶片老化方法
公开(公告)号：US06388460B1
公开(公告)日：2002-05-14
申请号：US09698713
申请日：2000-10-27
申请人： Walx Fang , Charlie Han
发明人： Walx Fang , Charlie Han
IPC分类号： G01F3102
CPC分类号： G01R31/318511 , G01R31/2879 , G01R31/318505 , G11C29/006 , G11C29/56012 , G11C2029/1204
摘要： An alternate-timing burn-in method suitable for testing a plurality of memory units on a wafer and capable of preventing any idling due to direct current timing. A first bit line voltage clocking signal is generated and sent to one terminal of any memory unit. A second bit line voltage clocking signal is generated and sent to the other terminal of the same memory unit. In addition, the edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal.
摘要翻译：一种适用于测试晶片上的多个存储器单元并且能够防止由于直流定时引起的空转的替代定时老化方法。产生第一位线电压计时信号并将其发送到任何存储器单元的一个端子。产生第二位线电压时钟信号并将其发送到同一存储器单元的另一端。此外，第二位线电压计时信号的边沿对应于第一位线电压计时信号的中点。

100. 发明申请

US20020047724A1 Multi-state test structures and methods 有权
标题翻译：多状态测试结构和方法
公开(公告)号：US20020047724A1
公开(公告)日：2002-04-25
申请号：US09965452
申请日：2001-09-26
发明人： Andrew Marshall , George E. Harris
IPC分类号： G01R031/26
CPC分类号： G01R31/318505 , G01R31/318511 , H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A test selector that multiplexes different test structures (202) to an adjacent probe pad (206) in dependence on the probe voltage.
摘要翻译：测试选择器，其根据探针电压将不同的测试结构（202）复用到相邻探针焊盘（206）。

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