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91. 发明授权

US09379222B2 Method of making a split gate non-volatile memory (NVM) cell 有权
标题翻译：制造分离门非易失性存储器（NVM）单元的方法
公开(公告)号：US09379222B2
公开(公告)日：2016-06-28
申请号：US14291320
申请日：2014-05-30
申请人： Brian A. Winstead , Konstantin V. Loiko
发明人： Brian A. Winstead , Konstantin V. Loiko
IPC分类号： H01L29/66 , H01L29/423 , H01L29/49 , H01L21/28 , H01L21/3213 , H01L21/306 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , H01L21/28035 , H01L21/28282 , H01L21/30625 , H01L21/32133 , H01L29/42332 , H01L29/42344 , H01L29/4916 , H01L29/66545 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： Making a non-volatile memory (NVM) structure uses a semiconductor substrate. One embodiment includes forming a select gate structure including a first dummy material on the semiconductor substrate and forming a control gate structure including a second dummy material on the semiconductor substrate, where the first dummy material is different from the second dummy material. The embodiment also includes replacing the first dummy material with metal and replacing the second dummy material with polysilicon.
摘要翻译：制造非易失性存储器（NVM）结构使用半导体衬底。一个实施例包括在半导体衬底上形成包括第一虚拟材料的选择栅极结构，并在半导体衬底上形成包括第二虚拟材料的控制栅极结构，其中第一虚拟材料与第二虚拟材料不同。该实施例还包括用金属代替第一虚拟材料并用多晶硅代替第二虚拟材料。

92. 发明授权

US09379035B1 IC package having non-horizontal die pad and lead frame therefor 有权
标题翻译： IC封装具有非水平管芯焊盘和引线框架
公开(公告)号：US09379035B1
公开(公告)日：2016-06-28
申请号：US14850966
申请日：2015-09-11
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： You Ge , Meng Kong Lye , Zhijie Wang
IPC分类号： H01L23/52 , H01L23/367 , H01L23/053 , H01L25/065 , H01L23/495 , H01L21/56 , H01L23/00
CPC分类号： H01L23/367 , H01L23/04 , H01L23/24 , H01L23/49541 , H01L23/49551 , H01L23/49568 , H01L23/49575 , H01L24/49 , H01L24/85 , H01L25/065 , H01L2224/45014 , H01L2924/00014 , H01L2924/15158 , H01L2224/45015 , H01L2924/207
摘要： A multi-component integrated circuit (IC) package has a base component (e.g., an interposer) defining a base of the IC package, a plurality of die pads extending from the base and forming side walls of the IC package, one or more IC dies, each mounted on an interior surface of one of the die pads, and bond wires electrically connecting the IC dies to another component of the IC package, such as the interposer or another die. By mounting dies on non-horizontal side walls, the IC package can provide more-effective thermal dissipation than conventional 3D IC packages having stacks of IC dies.
摘要翻译：多组分集成电路（IC）封装具有限定IC封装的基极的基底部件（例如插入件），从基座延伸并形成IC封装的侧壁的多个管芯焊盘，一个或多个IC 每个管芯安装在一个管芯焊盘的内表面上，以及将IC芯片电连接到IC封装的另一部件（例如插入器或另一管芯）的接合线。通过将模具安装在非水平侧壁上，IC封装可以提供比具有IC芯片堆叠的常规3D IC封装更有效的散热。

93. 发明授权

US09378325B2 Method and apparatus for performing integrated circuit layout verification 有权
标题翻译：用于执行集成电路布局验证的方法和装置
公开(公告)号：US09378325B2
公开(公告)日：2016-06-28
申请号：US14380384
申请日：2012-02-23
申请人： Xavier Hours , Shitiz Arora , Robert Scott Ruth
发明人： Xavier Hours , Shitiz Arora , Robert Scott Ruth
IPC分类号： G06F17/50 , H01L21/027
CPC分类号： G06F17/5081 , H01L21/027 , Y02T10/82
摘要： A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localized layout information for the at least one IC component from the received layout information, defining the localized layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.
摘要翻译：描述了对集成电路（IC）布局执行布局验证的方法。该方法包括接收IC布局的布局信息，识别IC布局内的至少一个IC组件，从接收到的布局信息中提取至少一个IC组件的局部布局信息，为该至少一个IC定义局部布局信息组件，并且至少部分地基于所述至少一个组件实例参数，对所述至少一个组件执行至少一个布局验证检查。

94. 发明授权

US09377504B2 Integrated circuit interconnect crack monitor circuit 有权
标题翻译：集成电路互连裂纹监测电路
公开(公告)号：US09377504B2
公开(公告)日：2016-06-28
申请号：US14227225
申请日：2014-03-27
申请人： Stanley A. Cejka , Steven A. Atherton , William J. Downey , James C. Golab , Brian D. Young
发明人： Stanley A. Cejka , Steven A. Atherton , William J. Downey , James C. Golab , Brian D. Young
IPC分类号： H01L23/52 , G01R31/28 , H01L23/00 , H01L23/498
CPC分类号： G01R31/2818 , G01R31/2812 , G01R31/2882 , G01R31/2896 , H01L22/34 , H01L23/49816 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/1319 , H01L2224/14179 , H01L2224/16227 , H01L2224/45014 , H01L2224/48227 , H01L2224/4847 , H01L2224/852 , H01L2224/85205 , H01L2924/00014 , H01L2924/30101 , H01L2924/351 , H05K1/141 , H05K3/3436 , H01L2924/014 , H01L2224/45099 , H01L2924/01082 , H01L2924/01047 , H01L2924/01029 , H01L2924/0781 , H01L2924/00012
摘要： A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.
摘要翻译：安装在基板上的电路装置包括检测电路，其检测返回信号的特性，以确定装置的各种互连的完整性。

95. 发明申请

US20160180891A1 SEMICONDUCTOR WAFER AND METHOD OF FABRICATING AN IC DIE 有权
标题翻译：半导体晶圆和制造IC芯片的方法
公开(公告)号：US20160180891A1
公开(公告)日：2016-06-23
申请号：US14574597
申请日：2014-12-18
申请人： ROBERT F. MORAN , DEREK BEATTIE , MARK MAIOLANI
发明人： ROBERT F. MORAN , DEREK BEATTIE , MARK MAIOLANI
IPC分类号： G11C5/02 , G11C8/10 , H01L23/528 , H01L21/82 , H01L27/02 , G11C5/06 , G11C7/10
CPC分类号： G11C5/025 , G11C5/066 , G11C7/10 , G11C7/1003 , H01L21/82 , H01L23/528 , H01L25/0657 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules.There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.
摘要翻译：提供了包括多个复制IC模块的半导体晶片。每个复制的IC模块能够形成单个IC芯片。半导体晶片还包括模块间晶片间电连接，并且复制IC模块还被布置成被切割成包括多个复制IC模块的IC模具。还提供了一种制造IC芯片的方法。该方法包括制造这样的半导体晶片，确定复制IC模块的所需配置，识别沿其切割半导体晶片以实现复制IC模块所需配置的模块间边界，以及沿着所识别的间隔区切割半导体晶片，模块边界以产生至少一个包含复制IC模块所需配置的IC芯片。

96. 发明授权

US09374051B2 Phase shift and attenuation circuits for use with multiple-path amplifiers 有权
标题翻译：用于多路径放大器的相移和衰减电路
公开(公告)号：US09374051B2
公开(公告)日：2016-06-21
申请号：US14728196
申请日：2015-06-02
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Abdulrhman M. S Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
IPC分类号： H03F3/68 , H03F1/02 , H03F3/21 , H03F3/60 , G06G7/10 , H03F3/189 , H04L7/00
CPC分类号： H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
摘要： Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
摘要翻译：与包括多个放大器路径的放大器一起使用的电路的实施例包括与第一电路并联的第一电路和第二电路。第一电路包括耦合到第一功率分配器输出的第一输入，耦合到多个放大器路径的第一放大器路径的第一输出以及耦合在第一输入和第一输出之间的第一可调移相器和第一衰减器串联。第二电路包括耦合到第二功率分配器输出的第二输入，耦合到多个放大器路径的第二放大器路径的第二输出以及耦合在第二输入和第二输出之间的第二可调相移器。

97. 发明授权

US09372729B2 Task scheduling method and apparatus 有权
标题翻译：任务调度方法和装置
公开(公告)号：US09372729B2
公开(公告)日：2016-06-21
申请号：US13833509
申请日：2013-03-15
申请人： Mihai-Daniel Fecioru
发明人： Mihai-Daniel Fecioru
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4881 , G06F9/4887
摘要： An apparatus schedules execution of a plurality of tasks by a processor. Each task has an associated periodicity and an associated priority based upon the associated periodicity. The processor executes each of the plurality of tasks periodically according to the associated periodicity of the task. A scheduler, at each of a series of scheduling time points updates the priorities of the plurality of tasks and schedules the tasks that need to be executed in accordance with their priorities. The scheduler identifies an unexecuted task which, at a preceding scheduling time point, was scheduled for execution but which, since that preceding scheduling time point, has not been executed. The scheduler sets the priority of the unexecuted task as greater than the priority of other tasks that have the same periodicity as the unexecuted task and that are not themselves unexecuted tasks.
摘要翻译：一种装置由处理器调度多个任务的执行。每个任务具有相关联的周期性和相关联的优先权，基于相关的周期性。处理器根据相关联的任务周期周期性地执行多个任务中的每一个。调度器在一系列调度时间点中的每一个时刻更新多个任务的优先级，并根据其优先级调度需要执行的任务。调度器识别未执行的任务，其在先前的调度时间点被调度为执行，但是由于该前一调度时间点尚未被执行。调度程序将未执行任务的优先级设置为大于具有与未执行任务相同周期性的其他任务的优先级，并且本身不是未执行的任务。

98. 发明授权

US09372723B2 System and method for conditional task switching during ordering scope transitions 有权
标题翻译：在订购范围转换期间进行条件任务切换的系统和方法
公开(公告)号：US09372723B2
公开(公告)日：2016-06-21
申请号：US14231784
申请日：2014-04-01
申请人： Zheng Xu , Tommi M. Jokinen , William C. Moyer
发明人： Zheng Xu , Tommi M. Jokinen , William C. Moyer
IPC分类号： G06F9/48
CPC分类号： G06F9/4843 , G06F9/461 , G06F9/48
摘要： A data processing system includes a processor core and ordering scope manager circuitry. The processor core sends an indication of a first ordering scope identifier for a current ordering scope a task currently being executed by the processor core and a second ordering scope identifier for a next-in-order ordering scope of the task. The ordering scope manager receives the indication the first and second ordering scope identifiers from processor core, and, provides a no task switch indicator to the processor core in response to determining that the first task is a first-in-transition-order task for the first ordering scope identifier and that processor core is authorized to execute the next-in-order ordering scope. The processor core transitions from executing in the current ordering scope to executing in the next-in-order ordering scope without performing task switch in response to the no task switch indicator being provided.
摘要翻译：数据处理系统包括处理器核心和订购范围管理器电路。处理器核心向当前订购范围发送当前由处理器核心执行的任务的第一订购范围标识符和用于任务的下一个订购范围的第二订购范围标识符的指示。订购范围管理器从处理器核心接收第一和第二订购范围标识符的指示，并且响应于确定第一任务是第一个转换顺序任务，向处理器核心提供无任务切换指示符第一个订购范围标识符，该处理器核心被授权执行下一个订购范围。处理器核心从当前订购范围内的执行转变为按顺序排序范围执行，而不响应于提供无任务切换指示器而执行任务切换。

99. 发明申请

US20160172867A1 CONTROL OF POWER TRANSFER 审中-公开
标题翻译：电力传输控制
公开(公告)号：US20160172867A1
公开(公告)日：2016-06-16
申请号：US14568250
申请日：2014-12-12
申请人： STANISLAV ARENDARIK , VACLAV HALBICH
发明人： STANISLAV ARENDARIK , VACLAV HALBICH
IPC分类号： H02J5/00 , H02J17/00
CPC分类号： H02J17/00 , H02J50/10
摘要： An apparatus comprising: a first transmitter configured to transmit in a first channel defined by a first frequency band; a second transmitter configured to transmit in a second channel defined by a second frequency band; and a controller configured to control power transfer via the first channel in dependence upon an impedance of the first channel and an impedance of the second channel.
摘要翻译：一种装置，包括：第一发射机，被配置为在由第一频带限定的第一信道中进行发射; 第二发射机，被配置为在由第二频带限定的第二信道中进行发射; 以及控制器，被配置为根据第一通道的阻抗和第二通道的阻抗来控制经由第一通道的功率传递。

100. 发明申请

US20160172199A1 NANOCRYSTAL MEMORY AND METHODS FOR FORMING SAME 有权
标题翻译：纳米晶体存储器及其形成方法
公开(公告)号：US20160172199A1
公开(公告)日：2016-06-16
申请号：US14568155
申请日：2014-12-12
申请人： Cheong Min Hong , Euhngi Lee
发明人： Cheong Min Hong , Euhngi Lee
IPC分类号： H01L21/28
CPC分类号： H01L21/28282 , H01L21/28273 , H01L27/11517 , H01L27/11563 , H01L29/42328 , H01L29/42332 , H01L29/7881
摘要： A charge-storing device includes a charge-storing layer including nanocrystals. The nanocrystals are formed by a deposition technique incorporating deuterated hydrides. The deuterated hydride can be used to form an amorphous semiconductor material that is annealed to form nanoparticles to be incorporated into the charge-storing layer.
摘要翻译：电荷存储装置包括具有纳米晶体的电荷存储层。纳米晶体通过结合氘代氢化物的沉积技术形成。氘代氢化物可用于形成非晶半导体材料，其被退火以形成要并入电荷存储层的纳米颗粒。

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