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91. 发明申请

US20130115846A1 SELF ASSEMBLY OF FIELD EMISSION TIPS BY CAPILLARY BRIDGE FORMATIONS 有权
标题翻译：自发组件通过毛细管桥形成的场发射提示
公开(公告)号：US20130115846A1
公开(公告)日：2013-05-09
申请号：US13291593
申请日：2011-11-08
申请人： Sanjiv Sambandan , John E. Northrup , Gregory L. Whiting , Robert A. Street
发明人： Sanjiv Sambandan , John E. Northrup , Gregory L. Whiting , Robert A. Street
IPC分类号： H01J9/04
CPC分类号： H01J9/025 , H01J2329/0415
摘要： A first side has a first surface on which is located a material, at least a portion of which is to be formed into at least one tip. A second side has a second surface which is heated. At least one of the first and second surfaces being moved so material located on the first surface comes into physical contact with the second surface. Then at least one of the first side and the second side are moved, wherein the physical contact between the material and the second surface is maintained, causing the material to stretch between the second surface and the first surface, generating at least one capillary bridge. Movement is continued until the physical contact between the material and the second surface is broken resulting in the formation of at least one sharp conductive tip.
摘要翻译：第一侧面具有第一表面，其上定位有材料，其至少一部分将形成至少一个尖端。第二面具有被加热的第二表面。第一和第二表面中的至少一个被移动，使得位于第一表面上的材料与第二表面物理接触。然后移动第一侧面和第二侧面中的至少一个，其中保持材料和第二表面之间的物理接触，使材料在第二表面和第一表面之间拉伸，产生至少一个毛细管桥。继续移动，直到材料和第二表面之间的物理接触被破坏，从而形成至少一个尖锐的导电尖端。

92. 发明授权

US08268725B2 Horizontal coffee-stain method using control structure to pattern self-organized line structures 有权
标题翻译：使用控制结构的水平咖啡染色方法来模拟自组织线结构
公开(公告)号：US08268725B2
公开(公告)日：2012-09-18
申请号：US12900417
申请日：2010-10-07
申请人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
发明人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
IPC分类号： H01L21/288
CPC分类号： B82Y40/00 , B05D1/185 , H01L21/288 , H01L21/76838 , H01L29/40 , H01L51/0022 , H01L51/0508
摘要： A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
摘要翻译：一种用于生产自组织线结构和其它非常精细特征的改进的咖啡染色方法，其涉及在目标基底上设置溶液池，然后使用接触水坑上表面的控制结构来控制熔池的外围边界形状。溶液由分散在液体溶剂润湿剂中的细颗粒溶质组成，并被固定到靶基质和对照结构两者上。然后使溶剂以预定的速率蒸发，使得溶质的一部分在目标衬底表面上形成与周边水泥边界接触的自组织的“咖啡污渍”线结构。目标结构可选地周期性地升高以产生随后被处理以形成例如用于大面积电子器件的TFT的平行线。

93. 发明授权

US08158973B2 Organic memory array with ferroelectric field-effect transistor pixels 有权
标题翻译：具有铁电场效应晶体管像素的有机存储阵列
公开(公告)号：US08158973B2
公开(公告)日：2012-04-17
申请号：US12607890
申请日：2009-10-28
申请人： Tse Nga Ng , Ana C. Arias , Sanjiv Sambandan , Robert A. Street , Jurgen H. Daniel
发明人： Tse Nga Ng , Ana C. Arias , Sanjiv Sambandan , Robert A. Street , Jurgen H. Daniel
IPC分类号： H01L51/10
CPC分类号： H01L27/283 , B82Y10/00 , G11C11/22 , G11C13/0014 , H01L27/11507 , H01L27/286
摘要： An organic non-volatile memory array including multiple pixels and associated signal lines that are disposed on and between a substrate, a single ferroelectric dielectric layer, and a single organic dielectric layer, where each pixel includes a ferroelectric field-effect transistor (FeFET) and at least one organic thin-film field effect transistor (FET) that are connected to associated signal lines in a way that facilitates addressable reading and writing to the FeFET of a selected pixel without disturbing the data stored in adjacent pixels. Analog data storage in the FeFET array is also introduced that does not require analog-to-digital conversion of the stored data.
摘要翻译：一种有机非易失性存储器阵列，包括设置在衬底，单个铁电电介质层和单个有机电介质层之间和之间的多个像素和相关联的信号线，其中每个像素包括铁电场效应晶体管（FeFET）和至少一个有机薄膜场效应晶体管（FET），其以促进可寻址的读取和写入所选像素的FeFET的方式连接到相关联的信号线，而不会干扰存储在相邻像素中的数据。还引入了FeFET阵列中的模拟数据存储，不需要对存储的数据进行模数转换。

94. 发明申请

US20120037992A1 PRINTED TFT AND TFT ARRAY WITH SELF-ALIGNED GATE 有权
标题翻译：带自对准门的打印TFT和TFT阵列
公开(公告)号：US20120037992A1
公开(公告)日：2012-02-16
申请号：US13280407
申请日：2011-10-25
申请人： Robert A. Street
发明人： Robert A. Street
IPC分类号： H01L29/786
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1292 , H01L29/66742 , H01L29/786
摘要： A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact.
摘要翻译：使用一种方法来形成自对准薄膜晶体管。薄膜晶体管包括形成有状态切换材料的栅极触点和用于隔离栅极接触的介电层。源极 - 漏极层，其包括源极接触和漏极接触，形成有源极 - 漏极材料。栅极接触的区域暴露于能量的形式，其中能量将状态可切换材料的一部分从非导电材料转变为导电材料，导电部分限定栅极接触。源极触点和漏极触点之间形成半导体材料。

95. 发明申请

US20110185322A1 METHOD OF IN-PROCESS INTRALAYER YIELD DETECTION, INTERLAYER SHUNT DETECTION AND CORRECTION 有权
标题翻译：进程内部检测方法，中间层检测和校正
公开(公告)号：US20110185322A1
公开(公告)日：2011-07-28
申请号：US12693019
申请日：2010-01-25
申请人： Michael Yu Tak Young , Scott Jong Ho Limb , William S. Wong , Robert A. Street
发明人： Michael Yu Tak Young , Scott Jong Ho Limb , William S. Wong , Robert A. Street
IPC分类号： G06F17/50 , G01R31/26
CPC分类号： G11C29/025 , G01R31/2853 , G11C2029/0403 , H01L22/14 , H01L22/20
摘要： A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
摘要翻译：提供了一种用于阵列型设备中的过程中产量评估和校正的系统和方法。该系统和方法包括测量各个GATE线路，DATA线路，DATA总线I / O焊盘和GATE总线I / O焊盘之间的电阻; 并分析测量的电阻以识别以下至少之一：GATE线路开路缺陷，GATE线路桥梁缺陷，DATA线路开路缺陷，DATA线路桥梁缺陷和层间分流缺陷。

96. 发明申请

US20110083728A1 Disordered Nanowire Solar Cell 审中-公开
标题翻译：无序纳米线太阳能电池
公开(公告)号：US20110083728A1
公开(公告)日：2011-04-14
申请号：US12579379
申请日：2009-10-14
申请人： Robert A. Street , William S. Wong
发明人： Robert A. Street , William S. Wong
IPC分类号： H01L31/0352 , H01L31/00 , H01L31/0376 , H01L31/0232
CPC分类号： H01L31/035227 , H01L31/075 , Y02E10/548
摘要： A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible.
摘要翻译：无序的纳米线太阳能电池包括设置在无序纳米线垫中的掺杂硅纳米线，形成在硅纳米线表面上的薄（例如50nm）的针涂层，以及设置在上层（例如，掺杂）层。无序纳米线垫在高温（例如450℃）下使用VLS处理从种子层生长，由此晶体硅纳米线呈现增强光散射的随机交织图案。由纳米线散射的光被p-i-n层吸收，导致例如电子沿着纳米线传递到第一电极层，并且空穴通过共形导电层到可选的上电极层。无序纳米线太阳能电池的制造是大面积兼容的。

97. 发明申请

US20100317160A1 HORIZONTAL COFFEE-STAIN METHOD USING CONTROL STRUCTURE TO PATTERN SELF-ORGANIZED LINE STRUCTURES 有权
标题翻译：使用控制结构绘制自组织线结构的水平咖啡 -
公开(公告)号：US20100317160A1
公开(公告)日：2010-12-16
申请号：US12485007
申请日：2009-06-15
申请人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
发明人： Sanjiv Sambandan , Robert A. Street , Ana Claudia Arias
IPC分类号： H01L21/336 , B05D3/02
CPC分类号： B82Y40/00 , B05D1/185 , H01L21/288 , H01L21/76838 , H01L29/40 , H01L51/0022 , H01L51/0508
摘要： A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.
摘要翻译：一种用于生产自组织线结构和其它非常精细特征的改进的咖啡染色方法，其涉及在目标基底上设置溶液池，然后使用接触水坑上表面的控制结构来控制熔池的外围边界形状。溶液由分散在液体溶剂润湿剂中的细颗粒溶质组成，并被固定到靶基质和对照结构两者上。然后使溶剂以预定的速率蒸发，使得溶质的一部分在目标衬底表面上形成与周边水泥边界接触的自组织的“咖啡污渍”线结构。目标结构可选地周期性地升高以产生随后被处理以形成例如用于大面积电子器件的TFT的平行线。

98. 发明申请

US20100201612A1 PHOTORECEPTOR WITH A TFT BACKPLANE FOR XEROGRAPHY WITHOUT A ROS SYSTEM 有权
标题翻译：具有不带ROS系统的XEROGRAPHY的TFT背板的摄像机
公开(公告)号：US20100201612A1
公开(公告)日：2010-08-12
申请号：US12366665
申请日：2009-02-06
申请人： Gregory McGuire , Vladislav Skorokhod , Robert A. Street
发明人： Gregory McGuire , Vladislav Skorokhod , Robert A. Street
IPC分类号： G09G3/36
CPC分类号： G03G15/32 , G03G15/04054 , G03G2215/0407
摘要： Systems and methods are described that facilitate eliminating a need for a raster output scanner (ROS) or laser when generating a latent image on a photoreceptor. An addressable backplane is employed, comprising an array of field effect transistors (e.g., silicon or organic thin film transistors, or TFTs), wherein each TFT corresponds to a single pixel on a charge transport layer on the photoreceptor surface. Latent image formation is performed by forming a surface potential using corona charging, and then directing free charge carriers toward the photoreceptor surface to reduce electrostatic potential in areas that need to be toned. TFTs in the array are individually addressed, or selected, to connect to a common ground, which allows photodischarge to occur only in selected areas (e.g., pixels associated with the selected TFTs). Once the array of TFTs is addressed, an LED light source emits light over the surface of the photoreceptor, and only the selected (grounded) TFTs permit their associated pixels to discharge. In this manner, a latent image is formed without a need for a bulky and expensive ROS.
摘要翻译：描述了系统和方法，其在光感受器上产生潜像时有助于消除对光栅输出扫描器（ROS）或激光器的需要。采用可寻址的背板，其包括场效应晶体管阵列（例如，硅或有机薄膜晶体管或TFT），其中每个TFT对应于感光体表面上的电荷传输层上的单个像素。通过使用电晕充电形成表面电位，然后将自由电荷载体引导到感光体表面来降低需要调色的区域中的静电潜力来进行潜在的图像形成。阵列中的TFT被单独寻址或选择以连接到公共地，这允许仅在选定区域（例如，与所选择的TFT相关联的像素）中发生光电荷放电。一旦解决了TFT阵列，LED光源就会在感光体的表面上发光，只有选定的（接地的）TFT允许其相关像素放电。以这种方式，形成潜像，而不需要庞大且昂贵的ROS。

99. 发明申请

US20090159971A1 PRINTED TFT AND TFT ARRAY WITH SELF-ALIGNED GATE 有权
标题翻译：带自对准门的打印TFT和TFT阵列
公开(公告)号：US20090159971A1
公开(公告)日：2009-06-25
申请号：US11959956
申请日：2007-12-19
申请人： Robert A. Street
发明人： Robert A. Street
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1292 , H01L29/66742 , H01L29/786
摘要： A method is used to form a self-aligning thin film transistor. The thin film transistor includes a gate contact formed with a state-switchable material, and a dielectric layer to isolate the gate contact. A source-drain layer, which includes a source contact, and a drain contact are formed with a source-drain material. An area of the gate contact is exposed to a form of energy, wherein the energy transforms a portion of the state switchable material from a non-conductive material to a conductive material, the conductive portion defining the gate contact. A semiconductor material is formed between the source contact and the drain contact.
摘要翻译：使用一种方法来形成自对准薄膜晶体管。薄膜晶体管包括形成有状态切换材料的栅极接触和用于隔离栅极接触的介电层。源极 - 漏极层，其包括源极接触和漏极接触，形成有源极 - 漏极材料。栅极接触的区域暴露于能量的形式，其中能量将状态可切换材料的一部分从非导电材料转变为导电材料，导电部分限定栅极接触。源极触点和漏极触点之间形成半导体材料。

100. 发明授权

US07358530B2 Thin-film transistor array with ring geometry 有权
标题翻译：具有环形几何形状的薄膜晶体管阵列
公开(公告)号：US07358530B2
公开(公告)日：2008-04-15
申请号：US10734429
申请日：2003-12-12
申请人： William S. Wong , Jeng Ping Lu , Alberto Salleo , Michael L. Chabinyc , Raj B. Apte , Robert A. Street
发明人： William S. Wong , Jeng Ping Lu , Alberto Salleo , Michael L. Chabinyc , Raj B. Apte , Robert A. Street
IPC分类号： H01L29/04
CPC分类号： H01L27/283 , H01L27/12 , H01L27/3262 , H01L27/3274 , H01L29/41733 , H01L29/78696 , H01L51/0541 , H01L51/0545
摘要： An improved transistor array for a display or sensor device is described. The display or sensor device includes a plurality of pixels. Each pixel includes a width and a length. Each pixel is addressed by a transistor. The transistor addressing each pixel has a channel with a channel width. Each channel width is greater than the width or length of the pixel being addressed. By fabricating transistors with extremely long channel widths, lower mobility semiconductor materials can easily be used to fabricate the display device.
摘要翻译：描述了用于显示器或传感器装置的改进的晶体管阵列。显示器或传感器装置包括多个像素。每个像素包括宽度和长度。每个像素由晶体管寻址。寻址每个像素的晶体管具有通道宽度。每个通道宽度大于要寻址的像素的宽度或长度。通过制造具有非常长的沟道宽度的晶体管，可以容易地使用低迁移率半导体材料来制造显示器件。

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