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91. 发明授权

US5986328A Buried contact architecture 失效
标题翻译：埋地联络架构
公开(公告)号：US5986328A
公开(公告)日：1999-11-16
申请号：US926694
申请日：1997-09-10
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L21/285 , H01L21/768 , H01L21/8244 , H01L29/40
CPC分类号： H01L27/11 , H01L21/28512 , H01L21/76895 , Y10S257/903
摘要： An method for the fabrication of an improved polysilicon buried contact is described. The contact is formed within a trench etched into the silicon substrate. The effective area of the contact is thereby increased over the conventional planar buried contact by an amount equal to the area of the trench walls. For sub-micron sized buried contacts and trenches 1000 to 3000 Angstroms deep this area can be twice that of the conventional planar buried contact. Contacts formed in this fashion are particularly beneficial in the manufacture of static-random-access memory, devices (SRAMs) through their application with local-interconnects. They afford a lower contact resistance, manifested by the greater effective contact area, as well as a much reduced risk of open or high resistive contacts due to photomask mis-alignment. The presence of the trench also results in a higher junction capacitance which affords a reduction in soft-error-rates, a notable concern for memory devices.
摘要翻译：描述了一种用于制造改进的多晶硅掩埋接触件的方法。接触形成在蚀刻到硅衬底中的沟槽内。因此，接触的有效面积比常规的平面埋入触点增加了相当于沟槽壁面积的量。对于亚微米尺寸的埋地触点和深度为1000至3000埃的沟槽，该区域可以是常规平面埋入触点的两倍。以这种方式形成的触点在通过其局部互连的应用中制造静态随机存取存储器（SRAM）是特别有益的。它们提供较低的接触电阻，表现为更大的有效接触面积，以及由于光掩模误配对而导致的开放或高电阻接触的风险大大降低。沟道的存在还导致更高的结电容，这降低了软错误率，这是存储器件的显着关注。

92. 发明授权

US5930633A Integrated butt-contact process in shallow trench isolation 失效
标题翻译：浅沟槽隔离中的集成对接接触过程
公开(公告)号：US5930633A
公开(公告)日：1999-07-27
申请号：US898975
申请日：1997-07-23
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L21/762 , H01L21/768 , H01L21/76 , H01L21/28
CPC分类号： H01L21/76232 , H01L21/76895
摘要： A new method of forming a butted contact in combination with a shallow trench isolation process is described. Shallow trench isolation areas are formed within the semiconductor substrate and filled with an oxide. A first photomask is formed having an opening larger than the butted contact to be formed and exposing a portion of at least one of the shallow trench isolation areas. The oxide is etched away within the shallow trench isolation area where it is exposed forming a misalignment trench wherein the exposed sidewall is adjacent to a P-well. A gate oxide layer is grown on the surface of the substrate and on the exposed sidewall of the misalignment trench. A first polysilicon layer is deposited overlying the gate oxide layer and filling the misalignment trench. The polysilicon and oxide layers are etched away to form gate electrodes and interconnection lines where a portion of the first polysilicon layer remains within the misalignment trench. A dielectric layer is deposited overlying the gate electrodes and lines. A second photomask is formed overlying the dielectric layer having an opening where the butted contact is to be made. The dielectric layer is etched away within the opening. A second layer of polysilicon is deposited within the opening to form a butted contact wherein the presence of the gate oxide layer within the misalignment trench prevents a short between the first and second polysilicon layers within the misalignment trench and the adjacent substrate.
摘要翻译：描述了与浅沟槽隔离工艺结合形成对接触点的新方法。在半导体衬底内形成浅沟槽隔离区，并填充氧化物。形成第一光掩模，其开口大于待形成的对接触点，并暴露至少一个浅沟槽隔离区域的一部分。在浅沟槽隔离区域内蚀刻出氧化物，在其中暴露的氧化物形成未对准沟槽，其中暴露的侧壁与P阱相邻。栅极氧化层生长在衬底的表面和未对准沟槽的暴露的侧壁上。第一多晶硅层沉积在栅极氧化物层上并填充不对准沟槽。蚀刻掉多晶硅和氧化物层以形成栅电极和互连线，其中第一多晶硅层的一部分保留在不对准沟槽内。沉积在栅电极和线上的电介质层。第二光掩模形成在具有开口的电介质层之上，其中对接触点将被制成。电介质层在开口内蚀刻掉。第二层多晶硅沉积在开口内以形成对接触点，其中在对准沟槽内的栅极氧化物层的存在防止不对准沟槽和相邻衬底内的第一和第二多晶硅层之间的短路。

93. 发明授权

US5915192A Method for forming shallow trench isolation 失效
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US5915192A
公开(公告)日：1999-06-22
申请号：US928280
申请日：1997-09-12
申请人： Jhon-Jhy Liaw , Jin-Yuan Lee
发明人： Jhon-Jhy Liaw , Jin-Yuan Lee
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A method of forming a trench isolation is disclosed. The initial step includes forming a first dielectric layer on a substrate of a transistor followed by a second dielectric layer formed on the first dielectric layer. Next, the substrate, the first dielectric layer and the second dielectric layer is patterned and etched to form a trench in the substrate, the first dielectric layer and the second dielectric layer. Next, a third dielectric layer is formed on the surface of the side wall of the trench followed by isotropically etching the bottom of the trench. Finally, a fourth dielectric layer on the surface of the trench is formed and the trench is filled with a dielectric material.
摘要翻译：公开了形成沟槽隔离的方法。初始步骤包括在晶体管的衬底上形成第一电介质层，随后形成在第一介电层上的第二电介质层。接下来，对衬底，第一电介质层和第二电介质层进行构图和蚀刻，以在衬底，第一介电层和第二电介质层中形成沟槽。接下来，在沟槽的侧壁的表面上形成第三电介质层，然后各向同性蚀刻沟槽的底部。最后，形成沟槽表面上的第四电介质层，并用电介质材料填充沟槽。

94. 发明授权

US5795827A Method for reducing the resistance of self-aligned contacts, for triple polysilicon SRAM devices 失效
标题翻译：用于降低自对准触点电阻的方法，用于三重多晶硅SRAM器件
公开(公告)号：US5795827A
公开(公告)日：1998-08-18
申请号：US783981
申请日：1997-01-15
申请人： Jhon-Jhy Liaw , Ding-Shan Wang
发明人： Jhon-Jhy Liaw , Ding-Shan Wang
IPC分类号： H01L21/60 , H01L21/8244 , H01L21/44
CPC分类号： H01L27/11 , H01L24/11 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/1306 , H01L2924/13091 , H01L2924/19043
摘要： A process for fabricating MOSFET devices, for a SRAM cell, using a polycide contact structure, self-aligned to an underlying source and drain region, has been developed. This process features the use of a high temperature, rapid thermal anneal step, used to dissolve native oxide at the polycide-source and drain interface, thus reducing the resistance at the interface of the polycide self-aligned structure, and the underlying source and drain area.
摘要翻译：已经开发了用于制造用于SRAM单元的MOSFET器件的工艺，其使用与底层源极和漏极区域自对准的多晶硅接触结构。该工艺特征在于使用高温快速热退火步骤，用于在天然氧化物源和漏极界面处溶解天然氧化物，从而降低了多阴离子自对准结构的界面处的电阻，以及底层的源极和漏极区。

95. 发明授权

US5554565A Modified BP-TEOS tungsten-plug contact process 失效
标题翻译：改良BP-TEOS钨插头接触工艺
公开(公告)号：US5554565A
公开(公告)日：1996-09-10
申请号：US606832
申请日：1996-02-26
申请人： Jhon-Jhy Liaw , Jin-Yuan Lee , Ming-Chang Teng
发明人： Jhon-Jhy Liaw , Jin-Yuan Lee , Ming-Chang Teng
IPC分类号： H01L21/768 , H01L21/441
CPC分类号： H01L21/76855 , H01L21/76801 , H01L21/76814 , H01L21/76877
摘要： An improved method for the fabrication of an ohmic, low resistance contact to heavily doped silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for surface planarizatiion by depositing first a layer of silicon oxide followed by a layer of borophosphosilicate glass onto a silicon wafer containing integrated circuit devices. After the glass is thermally flowed to planarize its surface, it is etched back to a suitable thickness and a second layer of silicon oxide is deposited over the now-planar surface. Contact holes are patterned in the composite silicon oxide-glass-silicon oxide structure and the exposed silicon device contacts are ion-implanted. The implant is then activated by rapid-thermal-annealing. The presence of the second silicon oxide layer prevents the upper corners of the contact openings from flowing and encroaching into the opening as would occur in its absence. Not only does this provide for void-free filling of the contact openings by the tungsten contact deposition but it also permits the use of higher temperatures for the implant anneal.
摘要翻译：使用具有Ti / TiN屏蔽冶金的CVD沉积钨插塞来描述用于制造对重掺杂硅的欧姆低电阻接触的改进方法。该方法通过首先沉积氧化硅层，然后通过一层硼磷硅酸盐玻璃沉积到含有集成电路器件的硅晶片上来提供表面平坦化。在玻璃被热流动以使其表面平坦化之后，将其回蚀刻到合适的厚度，并且在现在的平面表面上沉积第二层氧化硅。在复合氧化硅 - 玻璃 - 氧化硅结构中图案化接触孔，并且暴露的硅器件触点被离子注入。然后通过快速热退火激活植入物。第二氧化硅层的存在防止接触开口的上角流动并侵入开口，如在其不存在时将发生的那样。这不仅提供了通过钨接触沉积的无孔填充接触开口，而且还允许使用较高的温度进行注入退火。

96. 发明授权

US09036404B2 Methods and apparatus for SRAM cell structure 有权
标题翻译： SRAM单元结构的方法和装置
公开(公告)号：US09036404B2
公开(公告)日：2015-05-19
申请号：US13436149
申请日：2012-03-30
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C11/00 , G06F17/50 , G11C11/412 , H01L27/02 , H01L27/11
CPC分类号： H01L27/1104 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G11C11/412 , H01L27/0207 , H01L27/0924 , H01L27/11
摘要： An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.
摘要翻译：一个SRAM单元结构。在一个实施例中，在位线节点处，在位线条节点处，在数据节点处和在数据条上形成的位单元第一电平触点形成在第一和第二CVdd节点，第一和第二CVss节点节点; 以及形成在第一和第二CVdd节点，第一和第二CVss节点，位线节点和位线条节点上的每个第一级触点上的第二级触点; 其中形成在所述数据节点和所述数据条节点处的所述第一级触点不具有形成在其上的第二级触点。在另一个实施例中，形成字线，并且将位线和CVdd和CVss线形成在SRAM单元上并耦合到对应的节点。公开了形成电池结构的方法。

97. 发明授权

US08976573B2 Apparatus for SRAM cells 有权
标题翻译： SRAM单元的设备
公开(公告)号：US08976573B2
公开(公告)日：2015-03-10
申请号：US13446220
申请日：2012-04-13
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C5/02
CPC分类号： H01L27/1104 , G11C8/14 , G11C11/412 , H01L27/0207 , H01L29/785
摘要： A memory cell comprises a first word line in a first interconnect layer, a first VSS line, a first bit line, a power source line, a second bit line and a second VSS line formed a second interconnect layer, a second word line in a third interconnect layer. The memory cell further comprises a word line strap structure formed between the power source line and the second bit line, wherein the word line strap structure couples the first word line and the second word line.
摘要翻译：存储单元包括第一互连层中的第一字线，第一VSS线，第一位线，电源线，第二位线和形成第二互连层的第二VSS线，第二字线第三互连层。存储单元还包括形成在电源线和第二位线之间的字线带结构，其中字线条结构将第一字线和第二字线耦合。

98. 发明申请

US20130292777A1 Structure for FinFETs 有权
公开(公告)号：US20130292777A1
公开(公告)日：2013-11-07
申请号：US13463687
申请日：2012-05-03
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： H01L27/092 , H01L27/088
CPC分类号： H01L27/1116 , G11C11/412 , G11C11/419 , H01L27/0207 , H01L27/0886 , H01L27/0924 , H01L27/1104 , H01L29/0649 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/7848 , H01L29/7853 , H01L29/7855
摘要： An SRAM array is formed by a plurality of FinFETs formed by fin lines. Each fin line is formed in a substrate, wherein a bottom portion of the fin line is enclosed by an isolation region and an upper portion of the fin line protrudes above a top surface of the isolation region. From a first cross sectional view of the SRAM array, each fin line is of a rectangular shape. From a second cross sectional view of the SRAM array, the terminals of each fin line is of a tapered shape.

99. 发明申请

US20130258749A1 Apparatus for High Speed ROM Cells 有权
标题翻译：高速ROM单元的设备
公开(公告)号：US20130258749A1
公开(公告)日：2013-10-03
申请号：US13436452
申请日：2012-03-30
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C17/08
CPC分类号： H01L27/11213 , G11C5/02 , G11C5/06 , G11C5/063 , G11C11/412 , G11C17/08 , H01L27/0207 , H01L27/1124 , H01L29/785 , H01L2029/7858
摘要： A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is coupled to a first VSS line and a second VSS line formed in a first interconnect layer, wherein the second VSS line is electrically coupled to the first VSS line, and wherein the second VSS line is of a direction orthogonal to a direction of the first VSS line. The ROM cell further comprises a first bit line formed in the first interconnect layer, wherein the first bit line is formed in parallel with the second VSS line and a second bit line formed in the first interconnect layer, wherein the second bit line is formed in parallel with the second VSS line.
摘要翻译： ROM单元包括形成在存储单元的晶体管的第一有源区上的第一第一级触点，形成在存储单元晶体管的第二有源区上的第二第一级触点，其中第二级接触件耦合到形成在第一互连层中的第一VSS线路和第二VSS线路，其中第二VSS线路电耦合到第一VSS线路，并且其中第二VSS线路与正交于第一VSS线路的方向正交的方向第一条VSS线。 ROM单元还包括形成在第一互连层中的第一位线，其中第一位线与第二VSS线并联形成，第二位线形成在第一互连层中，其中第二位线形成在与第二条VSS线并联。

100. 发明申请

US20130141962A1 Methods and Apparatus for finFET SRAM Arrays in Integrated Circuits 有权
标题翻译：集成电路中finFET SRAM阵列的方法和装置
公开(公告)号：US20130141962A1
公开(公告)日：2013-06-06
申请号：US13312810
申请日：2011-12-06
申请人： Jhon-Jhy Liaw
发明人： Jhon-Jhy Liaw
IPC分类号： G11C11/40
CPC分类号： G11C11/419 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods and apparatus for providing single finFET and multiple finFET SRAM arrays on a single integrated circuit. A first single port SRAM array of a plurality of first bit cells is described, each first bit cell having a y pitch Y1 and an X pitch X1, the ratio of X1 to Y1 being greater than or equal to 2, each bit cell further having single fin finFET transistors to form a 6T SRAM cell and a first voltage control circuit; and a second single port SRAM array of a plurality of second bit cells, each second bit cell having a y pitch Y2 and an X pitch X2, the ratio of X2 to Y2 being greater than or equal to 3, each of the plurality of second bit cells comprising a 6T SRAM cell wherein the ratio of X2 to X1 is greater than about 1.1.
摘要翻译：在单个集成电路上提供单个finFET和多个finFET SRAM阵列的方法和装置。描述了多个第一位单元的第一单端口SRAM阵列，每个第一位单元具有ay间距Y1和X间距X1，X1与Y1之比大于或等于2，每个位单元还具有单个鳍式finFET晶体管，形成6T SRAM单元和第一电压控制电路; 以及多个第二位单元的第二单端口SRAM阵列，每个第二位单元具有ay间距Y2和X间距X2，X2与Y2之比大于或等于3，所述多个第二位中的每一个包含6T SRAM单元的单元，其中X2与X1之比大于约1.1。

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