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91. 发明申请

US20090239358A1 Memory Device Manufacturing Method 有权
标题翻译：存储器件制造方法
公开(公告)号：US20090239358A1
公开(公告)日：2009-09-24
申请号：US12469184
申请日：2009-05-20
申请人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Chiahua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/28
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1253 , H01L45/14 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16
摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.
摘要翻译：制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。第一和第二电极形成在第一和第二表面上。存储元件形成在表面段上以电连接第一和第二电极。

92. 发明申请

US20090096017A1 STACKED THIN FILM TRANSISTOR, NON-VOLATILE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：堆叠薄膜晶体管，非易失性存储器件及其制造方法
公开(公告)号：US20090096017A1
公开(公告)日：2009-04-16
申请号：US12337289
申请日：2008-12-17
申请人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11578 , H01L27/1203 , H01L29/4234
摘要： A manufacturing method for stacked, non-volatile memory devices provides a plurality of bitline layers and wordline layers with charge trapping structures. The bitline layers have a plurality of bitlines formed on an insulating layer, such as silicon on insulator technologies. The wordline layers are patterned with respective pluralities of wordlines and charge trapping structures orthogonal to the bitlines.
摘要翻译：用于堆叠的非易失性存储器件的制造方法提供具有电荷俘获结构的多个位线层和字线层。位线层具有形成在绝缘层上的多个位线，例如绝缘体上硅技术。用相应的多个字线和与位线正交的电荷俘获结构对字线层进行构图。

93. 发明申请

US20070134855A1 A STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：堆叠的非易失性存储器件及其制造方法
公开(公告)号：US20070134855A1
公开(公告)日：2007-06-14
申请号：US11425959
申请日：2006-06-22
申请人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
发明人： Erh-Kun Lai , Hang-Ting Lue , Kuang-Yeu Hsieh
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/792
摘要： A stacked non-volatile memory device comprises a plurality of bitline and word line layers stacked on top of each other. The bitline layers comprise a plurality of bitlines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.
摘要翻译：堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。位线层包括可以使用先进的处理技术形成的多个位线，从而使设备的制造成本高效且成本有效。该器件可以配置为NAND操作。

94. 发明申请

US20060292800A1 ONO formation of semiconductor memory device and method of fabricating the same 有权
标题翻译： ONO形成半导体存储器件及其制造方法
公开(公告)号：US20060292800A1
公开(公告)日：2006-12-28
申请号：US11159269
申请日：2005-06-23
申请人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Yen-Hao Shih , Shih-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.
摘要翻译：一种制造非易失性存储器件的方法至少包括以下步骤。首先，提供形成有底部电介质层的基板。然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。该结构被热退火以推动间隔开的掺杂区域向外扩散。退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

95. 发明授权

US08927956B2 Resistance type memory device 有权
标题翻译：电阻型记忆装置
公开(公告)号：US08927956B2
公开(公告)日：2015-01-06
申请号：US12403186
申请日：2009-03-12
申请人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
发明人： Ming-Daou Lee , Chia-Hua Ho , Erh-Kun Lai , Kuang-Yeu Hsieh
IPC分类号： H01L45/00 , G11C11/00 , G11C13/00 , G11C11/54 , G11C11/14 , G11C11/56
CPC分类号： G11C11/54 , G11C11/14 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/32 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633 , Y10S438/972
摘要： A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.
摘要翻译：提供电阻型存储器件。电阻型存储器件包括第一和第二导体和金属氧化物层。金属氧化物层设置在第一和第二导体之间，电阻型存储装置被定义为第一电阻率。在向金属氧化物层施加第一脉冲电压之后，将电阻型存储器件定义为第二电阻率。在向金属氧化物层施加第二脉冲电压之后，将电阻型存储器件定义为第三电阻率。第二电阻率大于第一电阻率，第一电阻率大于第三电阻率。

96. 发明授权

US08704205B2 Semiconductor structure with improved capacitance of bit line 有权
标题翻译：具有改善位线电容的半导体结构
公开(公告)号：US08704205B2
公开(公告)日：2014-04-22
申请号：US13594353
申请日：2012-08-24
申请人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Kuang-Yeu Hsieh , Erh-Kun Lai , Yen-Hao Shih
IPC分类号： H01L47/00
CPC分类号： H01L27/11582 , H01L27/11548 , H01L27/11556 , H01L27/11575
摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
摘要翻译：具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。第一组晶体管结构在第一体积区域周围具有第一栅极。第一导线连接到第一栅极以控制施加到第一栅极的电压。

97. 发明授权

US08067762B2 Resistance random access memory structure for enhanced retention 有权
标题翻译：电阻随机存取存储器结构，增强保留
公开(公告)号：US08067762B2
公开(公告)日：2011-11-29
申请号：US11560723
申请日：2006-11-16
申请人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： ChiaHua Ho , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/1608 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1625
摘要： A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.
摘要翻译：描述了双稳态电阻随机存取存储器，用于增强电阻随机存取存储器件中的数据保持。电介质构件，例如底部电介质构件位于电阻随机存取存储器构件的下方，其改善了保留信息中的SET / RESET窗口。底部电介质构件的沉积通过等离子体增强化学气相沉积或通过高密度 - 等离子体化学气相沉积来进行。用于构造底部电介质构件的一种合适的材料是氧化硅。双稳态随机存取存储器包括设置在电阻随机存取构件和底部电极或底部接触插塞之间的底部电介质构件。附加层包括位线，顶部接触插塞和设置在电阻随机存取存储器构件顶表面上的顶部电极。顶部电极和电阻随机存取存储器构件的侧面基本上彼此对准。

98. 发明授权

US08022489B2 Air tunnel floating gate memory cell 有权
标题翻译：空中隧道浮动门存储单元
公开(公告)号：US08022489B2
公开(公告)日：2011-09-20
申请号：US11134155
申请日：2005-05-20
申请人： Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/788 , H01L27/108 , H01L27/11 , H01L27/112
CPC分类号： H01L27/115 , G11C16/0408 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/515
摘要： An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.
摘要翻译：空气隧道浮动栅极存储单元包括限定在衬底上的空气通道。在空气隧道上定义第一多晶硅层（浮栅）。氧化物层设置在第一多晶硅层上，使得氧化物层覆盖第一多晶硅层并限定空气通道的侧壁。用作字线的第二多晶硅层被定义在氧化物层上。还公开了一种制造空气通道浮动栅极存储单元的方法。在衬底上形成牺牲层。在牺牲层上形成第一多晶硅层。在第一多晶硅层上沉积氧化物层，使得氧化物层覆盖第一多晶硅层并限定牺牲层的侧壁。使用热磷酸（H 3 PO 4）浸渍来蚀刻掉牺牲层以形成空气通道。

99. 发明授权

US07816661B2 Air cell thermal isolation for a memory array formed of a programmable resistive material 有权
标题翻译：用于由可编程电阻材料形成的存储器阵列的空气电池热隔离
公开(公告)号：US07816661B2
公开(公告)日：2010-10-19
申请号：US11562122
申请日：2006-11-21
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L21/06 , H01L47/00
CPC分类号： H01L45/144 , G11C13/00 , G11C13/0004 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/1293 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element.
摘要翻译：存储器件包括：第一电极元件，其大体呈平面形式，具有内部接触表面。然后存在与第一电极元件间隔开的圆柱形盖层，以及具有与第一电极接触表面和盖层接触的接触表面的相变元件，其中相变元件的横向尺寸小于的第一电极元件和圆柱形盖层。第二电极元件延伸穿过盖层以与相变元件接触。与介电填充材料构成的盖层对准的侧壁在第一电极元件和盖层之间延伸，使得相变元件，第一电极元件的接触表面和侧壁限定气体充满的热隔离单元邻近相变元件。

100. 发明授权

US07718989B2 Resistor random access memory cell device 有权
标题翻译：电阻随机存取存储单元器件
公开(公告)号：US07718989B2
公开(公告)日：2010-05-18
申请号：US11617542
申请日：2006-12-28
申请人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , ChiaHua Ho , Kuang Yeu Hsieh
IPC分类号： H01L29/02
CPC分类号： H01L45/122 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/144 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.
摘要翻译：存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件材料。因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

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