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91. 发明授权

US07710149B1 Input buffer for multiple differential I/O standards 失效
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07710149B1
公开(公告)日：2010-05-04
申请号：US12190530
申请日：2008-08-12
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiabao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiabao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

92. 发明申请

US20060220703A1 Programmable high speed interface 有权
标题翻译：可编程高速接口
公开(公告)号：US20060220703A1
公开(公告)日：2006-10-05
申请号：US11446483
申请日：2006-06-02
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B1/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

93. 发明申请

US20050134332A1 Programmable high speed I/O interface 有权
标题翻译：可编程高速I / O接口
公开(公告)号：US20050134332A1
公开(公告)日：2005-06-23
申请号：US10886015
申请日：2004-07-06
申请人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： G06F3/00 , G06F13/38 , H03K19/0175 , H03K19/173 , H03K19/177 , H03K17/16
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

94. 发明授权

US06707399B1 Data realignment techniques for serial-to-parallel conversion 有权
标题翻译：用于串行到并行转换的数据重新对准技术
公开(公告)号：US06707399B1
公开(公告)日：2004-03-16
申请号：US10269370
申请日：2002-10-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
IPC分类号： H03M900
CPC分类号： H03M9/00
摘要： Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.
摘要翻译：提供了用于调整串并转换器中的数据字节之间边界的技术。串行数据的位被移入第一寄存器。然后，数据字节沿并行信号线移出第一寄存器，进入第二寄存器。从第一寄存器到第二寄存器的并行加载数据的时序确定并行数据字节边界。可以使用负载使能信号来移位并行数据字节之间的边界。可以改变负载使能信号的相位，以将数据字节之间的边界移位一个或多个位。然后可以将并行数据从第二寄存器加载到第三寄存器中。第三寄存器的数据输出信号与核心时钟信号同步，以确保第三寄存器输出的信号的足够的建立和保持时间。

95. 发明授权

US07586341B2 Programmable high-speed interface 有权
标题翻译：可编程高速接口
公开(公告)号：US07586341B2
公开(公告)日：2009-09-08
申请号：US11830831
申请日：2007-07-30
申请人： Bonnie L. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie L. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B1/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

96. 发明授权

US06911923B1 Data realignment techniques for serial-to-parallel conversion 失效
标题翻译：用于串行到并行转换的数据重新对准技术
公开(公告)号：US06911923B1
公开(公告)日：2005-06-28
申请号：US10769733
申请日：2004-01-29
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
IPC分类号： H03M9/00 , G06F1/04 , G06F1/24 , G06F13/12 , G06F13/38
CPC分类号： H03M9/00
摘要： Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.
摘要翻译：提供了用于调整串并转换器中的数据字节之间边界的技术。串行数据的位被移入第一寄存器。然后，数据字节沿并行信号线移出第一寄存器，进入第二寄存器。从第一寄存器到第二寄存器的并行加载数据的时序确定并行数据字节边界。可以使用负载使能信号来移位并行数据字节之间的边界。可以改变负载使能信号的相位，以将数据字节之间的边界移位一个或多个位。然后可以将并行数据从第二寄存器加载到第三寄存器中。第三寄存器的数据输出信号与核心时钟信号同步，以确保第三寄存器输出的信号的足够的建立和保持时间。

97. 发明授权

US07315188B2 Programmable high speed interface 有权
标题翻译：可编程高速接口
公开(公告)号：US07315188B2
公开(公告)日：2008-01-01
申请号：US11446483
申请日：2006-06-02
申请人： Bonnie L. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie L. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B1/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

98. 发明授权

US09111603B1 Systems and methods for memory controller reference voltage calibration 有权
标题翻译：内存控制器参考电压校准的系统和方法
公开(公告)号：US09111603B1
公开(公告)日：2015-08-18
申请号：US13409077
申请日：2012-02-29
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/14
摘要： An integrated circuit may include a memory controller that interfaces with memory via one or more ports. A given port may be coupled to a comparator that receives data signals from the memory and a reference voltage signal and produces a corresponding output signal that identifies whether the data signals are logic one signals or logic zero signals. The memory controller may include detection circuitry coupled to the port that produces a target reference voltage signal for calibration of the reference voltage signal. The memory controller may include circuitry that produces the reference voltage signal based on control signals received from control circuitry. The control circuitry may generate the control signals to calibrate the reference voltage signal based on the target reference voltage.
摘要翻译：集成电路可以包括经由一个或多个端口与存储器接口的存储器控制器。给定端口可以耦合到从存储器接收数据信号的比较器和参考电压信号，并产生相应的输出信号，其识别数据信号是逻辑一个信号还是逻辑零信号。存储器控制器可以包括耦合到端口的检测电路，其产生用于校准参考电压信号的目标参考电压信号。存储器控制器可以包括基于从控制电路接收的控制信号产生参考电压信号的电路。控制电路可以产生控制信号，以基于目标参考电压来校准参考电压信号。

99. 发明授权

US08593195B1 High performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US08593195B1
公开(公告)日：2013-11-26
申请号：US13614526
申请日：2012-09-13
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03H11/16
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

100. 发明授权

US08237475B1 Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop 有权
标题翻译：用于产生PVT补偿相位偏移以提高锁定环路精度的技术
公开(公告)号：US08237475B1
公开(公告)日：2012-08-07
申请号：US12248031
申请日：2008-10-08
申请人： Pradeep Nagarajan , Sean Shau-Tu Lu , Chiakang Sung , Joseph Huang , Yan Chong
发明人： Pradeep Nagarajan , Sean Shau-Tu Lu , Chiakang Sung , Joseph Huang , Yan Chong
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0814 , H03L7/0816
摘要： A circuit includes a locked loop and a phase offset circuit. The locked loop generates first control signals for controlling a first delay in the locked loop. The phase offset circuit delays an input signal by a second delay that is controlled by second control signals to generate a delayed signal. The phase offset circuit generates the second control signals by adjusting the first control signals to increase the accuracy of the delayed signal with respect to a target phase. The second control signals compensate for at least a portion of a change in the second delay that is caused by a variation in at least one of a process, a supply voltage, and a temperature of the circuit.
摘要翻译：电路包括锁定环和相位偏移电路。锁定环产生用于控制锁定环路中的第一延迟的第一控制信号。相位偏移电路延迟由第二控制信号控制的第二延迟的输入信号以产生延迟的信号。相位偏移电路通过调整第一控制信号来产生第二控制信号，以提高相对于目标相位的延迟信号的精度。第二控制信号补偿由电路的过程，电源电压和温度中的至少一个的变化引起的第二延迟的变化的至少一部分。

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