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91. 发明授权

US06287942B1 Hermetic chip and method of manufacture 有权
标题翻译：密封芯片和制造方法
公开(公告)号：US06287942B1
公开(公告)日：2001-09-11
申请号：US09518293
申请日：2000-03-03
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： H01L21301
CPC分类号： H01L24/05 , H01L21/56 , H01L23/291 , H01L23/3107 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01031 , H01L2924/01032 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , Y10S438/958 , Y10S438/959 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process the fully hermetic sealing of both sides and the edges of the semiconductor chip out the use of a separate package.
摘要翻译：一种完全密封的半导体芯片及其制造方法。本发明的半导体芯片通过使用适用于其上的合适的涂层（例如玻璃）在其两侧及其边缘上完全气密密封，以防止半导体芯片的环境攻击。本发明的完全密封的半导体芯片不需要使用用于芯片的气密密封的单独封装，从而减小这种芯片的尺寸。本发明的半导体芯片的制造方法提供了使用单独的封装完全密封半导体芯片的两侧和边缘的简单工艺。

92. 发明授权

US6002180A Multi chip module with conductive adhesive layer 失效
标题翻译：多芯片模块带导电胶层
公开(公告)号：US6002180A
公开(公告)日：1999-12-14
申请号：US65361
申请日：1998-04-23
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L21/56 , H01L21/60 , H01L23/13 , H05K3/32 , H05K3/40 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/83 , H01L21/563 , H01L23/13 , H01L24/29 , H01L24/81 , H01L2224/1319 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/73203 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/30105 , H05K3/321 , H05K3/4007
摘要： A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.
摘要翻译：提供了一种用于形成诸如多芯片模块或存储器模块的芯片模块的方法。多芯片模块包括被配置为在其上安装多个半导体晶片的衬底。衬底包括形成为对应于骰子上的接合焊盘的位置的图案的凸起接触构件。在基板上的接触构件和骰子上的接合垫之间形成各向异性导电粘合剂层，以将骰子固定到基板上并在其间形成电连接。此外，可以在骰子和衬底之间形成底部填充层以填充它们之间的间隙，并进一步将骰子固定到衬底上。形成在基板上的导体和输入/输出焊盘形成到和接触构件的电路。为了形成存储器模块，可以将一个或多个多芯片模块安装到具有与导体电连通的边缘连接器和基板上的接触部件的支撑基板。

93. 发明授权

US5789278A Method for fabricating chip modules 失效
标题翻译：制造芯片模块的方法
公开(公告)号：US5789278A
公开(公告)日：1998-08-04
申请号：US688368
申请日：1996-07-30
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L21/56 , H01L21/60 , H01L23/13 , H05K3/32 , H05K3/40 , H01L21/44
CPC分类号： H01L24/83 , H01L21/563 , H01L23/13 , H01L24/29 , H01L24/81 , H01L2224/1319 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/73203 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/30105 , H05K3/321 , H05K3/4007
摘要： A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.
摘要翻译：提供了一种用于形成诸如多芯片模块或存储器模块的芯片模块的方法。多芯片模块包括被配置为在其上安装多个半导体晶片的衬底。衬底包括形成为对应于骰子上的接合焊盘的位置的图案的凸起接触构件。在基板上的接触构件和骰子上的接合垫之间形成各向异性导电粘合剂层，以将骰子固定到基板上并在其间形成电连接。此外，可以在骰子和衬底之间形成底部填充层以填充它们之间的间隙，并进一步将骰子固定到衬底上。形成在基板上的导体和输入/输出焊盘形成到和接触构件的电路。为了形成存储器模块，可以将一个或多个多芯片模块安装到具有与导体电连通的边缘连接器和基板上的接触部件的支撑基板。

94. 发明授权

US07855140B2 Method of forming vias in semiconductor substrates and resulting structures 有权
标题翻译：在半导体衬底和结构中形成通孔的方法
公开(公告)号：US07855140B2
公开(公告)日：2010-12-21
申请号：US11781083
申请日：2007-07-20
申请人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
发明人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898
摘要： Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.
摘要翻译：公开了在半导体衬底中形成贯通孔的方法和所得到的结构。在一个实施例中，可以通过从活性表面通过其上的导电元件和导电元件下面的基底的一部分形成部分通孔来形成通孔。然后可以通过从后表面的激光烧蚀或钻孔来完成通孔。在另一个实施例中，部分通孔可以通过激光烧蚀或从衬底的背面钻孔到其中的预定距离来形成。通孔可以通过形成延伸通过导电元件和下面的衬底以与激光钻孔的部分通孔相交的部分通孔从活性表面完成。在另一个实施例中，可以首先通过激光烧蚀或从衬底的背面进行钻孔形成部分通孔，然后通过干蚀刻来完成通孔。

95. 发明授权

US07093358B2 Method for fabricating an interposer 有权
标题翻译：中介层的制造方法
公开(公告)号：US07093358B2
公开(公告)日：2006-08-22
申请号：US10648163
申请日：2003-08-26
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01R43/16
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.
摘要翻译：一种插入器，其包括接纳半导体器件（例如倒装芯片型半导体器件）与栅介质基板的栅栏。栅栏可以包括被配置为使半导体器件与插入器衬底逐渐对准的边缘。挡板还可以包括一个或多个侧向凹入区域，以便于半导体器件与插入器基板的粗略对准。围栏的制造方法包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备并且有助于识别材料在其上和周围的插入物基板的位置和取向应用于一层或多层以形成栅栏。结果，内插器基板不需要精确地机械对准。

96. 发明授权

US06833613B1 Stacked semiconductor package having laser machined contacts 有权
标题翻译：具有激光加工触点的堆叠半导体封装
公开(公告)号：US06833613B1
公开(公告)日：2004-12-21
申请号：US09961646
申请日：2001-09-25
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L2302
CPC分类号： H01L24/81 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/75 , H01L25/105 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/48227 , H01L2224/75 , H01L2224/81801 , H01L2224/82039 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H05K1/0306 , H05K1/112 , H05K3/0029 , H05K3/0032 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for semiconductor components such as dice, wafers and chip scale packages is provided. The interconnect includes a substrate, and patterns of contacts formed on a face side of the substrate adapted to electrically engage external contacts (e.g., bond pads, solder bumps) on the components. The interconnect also includes insulated conductive members through the substrate, which provide direct electrical paths from the interconnect contacts to a backside of the substrate. The conductive members can be formed by laser machining openings in the substrate, and then filling the openings with a conductive material (e.g., metal, conductive polymer). The conductive members can also include pads with contact balls, configured for electrical interface with a test apparatus, such as test carrier or wafer handler. The interconnect can be used to construct test systems for testing semiconductor components, or to construct chip scale packages and multi chip modules.
摘要翻译：提供了诸如骰子，晶片和芯片级封装的半导体元件的互连。互连包括衬底和形成在衬底的面侧上的触点图案，其适于电耦合组件上的外部触点（例如，接合焊盘，焊料凸块）。互连还包括通过衬底的绝缘导电构件，其提供从互连触点到衬底背面的直接电路径。导电构件可以通过在衬底中激光加工开口形成，然后用导电材料（例如金属，导电聚合物）填充开口。导电构件还可以包括具有接触球的焊盘，其被配置为与诸如测试载体或晶片处理器的测试装置电接口。互连可用于构建用于测试半导体元件的测试系统，或构建芯片级封装和多芯片模块。

97. 发明授权

US06815314B2 Hermetic chip and method of manufacture 失效
标题翻译：密封芯片和制造方法
公开(公告)号：US06815314B2
公开(公告)日：2004-11-09
申请号：US09923687
申请日：2001-08-06
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： H01L21306
CPC分类号： H01L24/05 , H01L21/56 , H01L23/291 , H01L23/3107 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01031 , H01L2924/01032 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , Y10S438/958 , Y10S438/959 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.

98. 发明授权

US06509647B2 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer 失效
公开(公告)号：US06509647B2
公开(公告)日：2003-01-21
申请号：US09733572
申请日：2000-12-08
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L2348
CPC分类号： H01L23/13 , G01R1/0466 , G01R1/0483 , H01L23/49827 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/16237 , H01L2224/8114 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15174 , H05K3/325 , H05K3/326 , H01L2224/05599
摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads.

99. 发明授权

US06492738B2 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer 失效
公开(公告)号：US06492738B2
公开(公告)日：2002-12-10
申请号：US09389862
申请日：1999-09-02
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L2348
CPC分类号： H01L23/13 , G01R1/0466 , G01R1/0483 , H01L23/49827 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/16237 , H01L2224/8114 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15174 , H05K3/325 , H05K3/326 , H01L2224/05599
摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads. In another embodiment, an apparatus for testing a bumped device having a plurality of conductive bumps includes a substrate having a plurality of contact pads distributed thereon and substantially alignable with the plurality of conductive bumps, and an anisotropically conductive layer disposed on the first surface and engageable with the plurality of conductive bumps to electrically couple each of the conductive bumps with a corresponding one of the contact pads. Alternately, the test apparatus may also include an alignment device or a bumped device handler. In another embodiment, a method of testing a bumped device includes engaging a plurality of contact pads with an anisotropically conductive layer, engaging the plurality of conductive bumps with the anisotropically conductive layer substantially opposite from and in approximate alignment with the plurality of contact pads, forming a plurality of conductive paths through the anisotropically conductive layer so that each of the conductive bumps is electrically coupled to one of the contact pads, and applying test signals through at least some of the contact pads and the conductive paths to at least some of the conductive bumps.

100. 发明授权

US06400172B1 Semiconductor components having lasered machined conductive vias 有权
标题翻译：半导体元件具有激光加工的导电通孔
公开(公告)号：US06400172B1
公开(公告)日：2002-06-04
申请号：US09475546
申请日：1999-12-30
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： G01R3126
CPC分类号： H05K1/112 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/49827 , H01L23/5389 , H01L25/105 , H01L2224/05001 , H01L2224/05023 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/16237 , H01L2224/82039 , H01L2225/1005 , H01L2924/01004 , H01L2924/01006 , H01L2924/01009 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H05K1/0306 , H05K3/0029 , H05K3/0032 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H01L2924/00 , H01L2224/05124 , H01L2924/00014 , H01L2224/05147 , H01L2924/013
摘要： A method for fabricating semiconductor components, such as packages, interconnects and test carriers, is provided. The method includes laser machining conductive vias for interconnecting contacts on the component, using a laser beam that is focused to produce a desired via geometry. The vias can include enlarged end portions to facilitate deposition of a conductive material during formation of the vias, and to provide an increased surface area for forming the contacts. For example, by focusing the laser beam at a midpoint of a substrate of the component, an hour glass via geometry is provided. Alternately, the laser beam can be focused at an exit point, or at an entry point of the substrate, to provide converging or diverging via geometries. The method can also include forming contact pins on the conductive vias by bonding and shaping metal wires using a wire bonding process, or a welding process.
摘要翻译：提供了一种制造诸如封装，互连和测试载体的半导体部件的方法。该方法包括激光加工用于使部件上的触点互连的导电通孔，使用聚焦以产生所需通孔几何形状的激光束。通孔可以包括扩大的端部，以便于在形成通孔期间沉积导电材料，并且提供用于形成触点的增加的表面积。例如，通过将激光束聚焦在部件的基板的中点处，提供了小时玻璃通孔几何形状。或者，激光束可以在出口点处或在基板的入口处聚焦，以提供会聚或发散的几何形状。该方法还可以包括通过使用引线接合工艺或焊接工艺接合和成形金属线来在导电通孔上形成接触引脚。

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