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91. 发明授权

US08254180B2 Methods of operating memories including characterizing memory cell signal lines 有权
标题翻译：操作存储器的方法，包括表征存储单元信号线
公开(公告)号：US08254180B2
公开(公告)日：2012-08-28
申请号：US13235995
申请日：2011-09-19
申请人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
发明人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C5/063 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： Methods of operating memories facilitate compensating for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Methods include selecting a memory cell signal line of a memory and characterizing the memory cell signal line by determining an RC time constant of the memory cell signal line.
摘要翻译：操作存储器的方法有助于补偿存储器单元信号线传播延迟，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。方法包括通过确定存储单元信号线的RC时间常数来选择存储器的存储单元信号线并表征存储单元信号线。

92. 发明授权

US08203886B2 Memory device reference cell programming method and apparatus 有权
标题翻译：存储器件参考单元编程方法和装置
公开(公告)号：US08203886B2
公开(公告)日：2012-06-19
申请号：US13047014
申请日：2011-03-14
申请人： Vishal Sarin , Frankie F. Roohparvar
发明人： Vishal Sarin , Frankie F. Roohparvar
IPC分类号： G11C16/06
CPC分类号： G11C7/14 , G11C11/5628 , G11C16/0483 , G11C2211/5634
摘要： Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.
摘要翻译：公开了存储器件和方法，例如那些有助于整个存储器单元阵列中的参考单元的分配方案的存储器件和方法。例如，一个这样的分配方案按行交错格式分配参考单元，其中每列包含单个参考单元。还公开了以重复或伪随机模式分配的多个参考小区的附加方案。

93. 发明授权

US08174919B2 Apparatus and method for increasing data line noise tolerance 有权
标题翻译：增加数据线噪声容限的装置和方法
公开(公告)号：US08174919B2
公开(公告)日：2012-05-08
申请号：US12914309
申请日：2010-10-28
申请人： Frankie F. Roohparvar , Chia-Shing Jason Yu , Jung-Sheng Hoei , Vishal Sarin
发明人： Frankie F. Roohparvar , Chia-Shing Jason Yu , Jung-Sheng Hoei , Vishal Sarin
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/12 , G11C16/24 , G11C16/26
摘要： Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source.
摘要翻译：公开了用于改善存储器中的噪声容限的电路和方法，例如包括通过向电压源提供较高数据线充电电压或通过向数据线充电电压提供更高数据线充电电压而使数据线偏置在正常阈值电压之上的电路当前来源。

94. 发明授权

US08127091B2 Programming memory cells with additional data for increased threshold voltage resolution 有权
标题翻译：用附加数据编程存储单元，以提高阈值电压分辨率
公开(公告)号：US08127091B2
公开(公告)日：2012-02-28
申请号：US12261124
申请日：2008-10-30
申请人： Vishal Sarin , Frankie F. Roohparvar
发明人： Vishal Sarin , Frankie F. Roohparvar
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C2211/5641
摘要： Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.
摘要翻译：提供了用于存储器件，存储器件和存储器系统的数据传输和/或编程的方法。根据至少一种这样的方法，将附加数据附加到原始数据，并将所得数据编程在所选存储单元中。附加数据增加了原始数据的程序阈值电压余量。附加的数据可以是原始数据或逻辑零的副本。当读取所选择的存储单元时，存储器控制电路可以只读取MSB字段中的原始数据，或者存储器控制电路可以读取整个编程数据，并忽略LSB字段。

95. 发明授权

US08125831B2 Sensing against a reference cell 有权
标题翻译：检测参考细胞
公开(公告)号：US08125831B2
公开(公告)日：2012-02-28
申请号：US12955419
申请日：2010-11-29
申请人： Frankie F. Roohparvar , Vishal Sarin
发明人： Frankie F. Roohparvar , Vishal Sarin
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C16/28
摘要： Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states.
摘要翻译：公开了存储器件，大容量存储器件和操作存储器的方法，诸如适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的那些。这种存储器件的编程可以包括在表示期望的位模式的范围内对目标阈值电压进行编程。读取这样的存储器件可以包括产生指示目标存储器单元的阈值电压的模拟数据信号。可以相对于参考单元感测目标存储器单元，包括连接到存储器单元的目标串的存储器单元的虚拟串，并且例如通过使用差分放大器来感测参考单元和目标单元之间的差异。这可能允许更广泛的电压范围用于数据状态。

96. 发明授权

US08107296B2 Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device 有权
标题翻译：缓解非易失性存储设备中的后台模式和程序干扰造成的数据损坏
公开(公告)号：US08107296B2
公开(公告)日：2012-01-31
申请号：US12912027
申请日：2010-10-26
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations.
摘要翻译：在所公开的实施例之一中，使用写入算法来消除由于存储器单元中的反向图案效应，单元到单元电容耦合和程序干扰引起的错误。要编程的原始数据在存储器单元的初始编程操作之前被调整。然后在另一个编程操作中将原始数据编程到存储器单元中。在替代实施例中，读取调整权重数据值与存储器单元的每个串联串相关联。权重数据值用于补偿在初始字线读取期间读取的数据。在每次读取和读取调整之后更新权重数据值，使得在随后的读取操作中使用经调整的权重数据值。

97. 发明授权

US08102706B2 Programming a memory with varying bits per cell 有权
标题翻译：为每个单元编程具有不同位数的存储器
公开(公告)号：US08102706B2
公开(公告)日：2012-01-24
申请号：US12769713
申请日：2010-04-29
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C7/16 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C29/021 , G11C29/028 , G11C2211/5641
摘要： Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability.
摘要翻译：适于接收和发送表示两个或多个位的模拟数据信号的存储器件，例如有助于相对于传送指示各个位的数据信号的器件的数据传输速率的增加。控制器和读/写通道将数字位模式转换为模拟数据信号，以便以特定位容量级存储在存储器阵列中，以便实现期望的可靠性水平。

98. 发明授权

US08085596B2 Reducing noise in semiconductor devices 有权
标题翻译：降低半导体器件的噪音
公开(公告)号：US08085596B2
公开(公告)日：2011-12-27
申请号：US11853578
申请日：2007-09-11
申请人： Vishal Sarin , Frankie F. Roohparvar , Jung Sheng Hoei
发明人： Vishal Sarin , Frankie F. Roohparvar , Jung Sheng Hoei
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3418
摘要： The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a reset voltage to a control gate of a semiconductor device for a period of time. The method further includes sensing the state of the semiconductor device after applying the reset voltage.
摘要翻译：本公开包括用于降低半导体器件中的噪声的方法，装置，模块和系统。一个方法实施例包括将复位电压施加到半导体器件的控制栅极一段时间。该方法还包括在施加复位电压之后感测半导体器件的状态。

99. 发明申请

US20110305090A1 MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE 有权
标题翻译：内存控制器自动校准，用于删除系统影响
公开(公告)号：US20110305090A1
公开(公告)日：2011-12-15
申请号：US13217492
申请日：2011-08-25
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/04 , G11C16/20 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
摘要翻译：通过向所选择的单元写入电压来执行存储器控制器的自校准。对所选单元格周围的相邻单元进行编程。在每个相邻的编程操作之后，读取所选择的单元上的电压，以确定由例如浮动栅极到浮置栅极耦合的系统偏移引起的任何电压变化。这些变化被平均并存储在表中作为用于调整由偏移表示的存储器的特定区域中的编程电压或读取电压的偏移。通过在不同温度下写入单元格并在不同温度读取来确定温度的自校准方法，以生成写入路径和读取路径的温度偏移表。这些偏移表用于在编程期间和读取期间调整与系统温度相关的偏移。

100. 发明申请

US20110289387A1 PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL 有权
标题翻译：将错误修正代码编入固态状态存储器件，其中每个单元有不同的位数
公开(公告)号：US20110289387A1
公开(公告)日：2011-11-24
申请号：US13195977
申请日：2011-08-02
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/1072 , G11C29/12005
摘要： Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
摘要翻译：在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

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