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91. 发明授权

US08773934B2 Power line compensation for flash memory sense amplifiers 有权
标题翻译：闪存读出放大器的电源线补偿
公开(公告)号：US08773934B2
公开(公告)日：2014-07-08
申请号：US11528748
申请日：2006-09-27
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C7/02 , G11C7/06 , G11C11/4091
CPC分类号： G11C7/062 , G11C5/147 , G11C7/02 , G11C7/06 , G11C7/065 , G11C7/067 , G11C11/4091 , G11C11/5642 , G11C16/28 , G11C16/30 , G11C2207/063 , G11C2211/5645
摘要： In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.
摘要翻译：一方面，本发明涉及一种用于补偿多电平存储器的读出放大器中的功率电平变化的存储器系统。例如，可以采用补偿电路来补偿提供给多电平存储器读出放大器的功率的电流或电压变化。作为另一示例，可以通过向电源施加偏置电压来实现补偿。另一个例子是配置有改进的输入共模电压范围的读出放大器。这样的读出放大器可以是两对和三对读出放大器。本发明的其它示例包括更简化的读出放大器配置和具有减小的漏电流的读出放大器。

92. 发明申请

US20130187707A1 Charge Pump Systems and Methods 有权
标题翻译：电荷泵系统和方法
公开(公告)号：US20130187707A1
公开(公告)日：2013-07-25
申请号：US13726522
申请日：2012-12-24
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

93. 发明申请

US20130107632A1 Mixed Voltage Non-volatile Memory Integrated Circuit With Power Saving 有权
标题翻译：具有省电的混合电压非易失性存储器集成电路
公开(公告)号：US20130107632A1
公开(公告)日：2013-05-02
申请号：US13286969
申请日：2011-11-01
申请人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C16/30 , G11C5/147 , G11C11/5628 , G11C16/08
摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.
摘要翻译：集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。第二电压小于第一电压。可在第一电压下操作的第一电路在集成电路管芯中。可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。检测来自第二管芯焊盘的电流的电路在集成电路管芯中。开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

94. 发明申请

US20130106391A1 Low Voltage, Low Power Bandgap Circuit 有权
标题翻译：低电压，低功耗带隙电路
公开(公告)号：US20130106391A1
公开(公告)日：2013-05-02
申请号：US13286843
申请日：2011-11-01
申请人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A bandgap voltage generating circuit for generating a bandgap voltage has an operational amplifier that has two inputs and an output. A current mirror circuit has at least two parallel current paths. Each of the current paths is controlled by the output from the operational amplifier. One of the current paths is coupled to one of the two inputs to the operational amplifier. A resistor divide circuit is connected to the other current path. The resistor divide circuit provides the bandgap voltage of the circuit.
摘要翻译：用于产生带隙电压的带隙电压产生电路具有具有两个输入和输出的运算放大器。电流镜电路具有至少两个平行电流路径。每个电流路径由运算放大器的输出控制。电流路径之一耦合到运算放大器的两个输入之一。电阻分压电路连接到另一个电流通路。电阻分压电路提供电路的带隙电压。

95. 发明授权

US08385147B2 Systems and methods of non-volatile memory sensing including selective/differential threshold voltage features 有权
标题翻译：非易失性存储器感测的系统和方法包括选择性/差分阈值电压特征
公开(公告)号：US08385147B2
公开(公告)日：2013-02-26
申请号：US12750628
申请日：2010-03-30
申请人： Hieu Van Tran , Samar Saha
发明人： Hieu Van Tran , Samar Saha
IPC分类号： G11C7/06 , H01L29/792
CPC分类号： G11C7/065 , G11C7/06 , G11C7/062 , G11C16/28 , H01L21/28282 , H01L21/823412 , H01L21/823807 , H01L29/1083 , H01L29/42368 , H01L29/4238 , H01L29/66833 , H01L29/7835 , H01L29/792
摘要： Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.
摘要翻译：公开了用于通过使用具有差分阈值电压的MOS晶体管提供选择性阈值电压特性的系统和方法。在一个示例性实施例中，提供了一种金属氧化物半导体器件，其包括半导体材料的衬底，其具有源极区，漏极区和它们之间的沟道区，沟道区上方的绝缘层和绝缘层的栅极部。此外，关于器件，绝缘层的形状和/或接合区域的形状或注入在栅极 - 漏极和栅极 - 源极结之间具有不同的尺寸，以提供不同的阈值电压他们。

96. 发明授权

US08270213B2 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US08270213B2
公开(公告)日：2012-09-18
申请号：US12962343
申请日：2010-12-07
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/12
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

97. 发明授权

US08072815B2 Array of non-volatile memory cells including embedded local and global reference cells and system 有权
标题翻译：阵列非易失性存储单元包括嵌入式本地和全局参考单元和系统
公开(公告)号：US08072815B2
公开(公告)日：2011-12-06
申请号：US12965504
申请日：2010-12-10
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.
摘要翻译：存储单元阵列具有与第一列相邻的第一侧，与第一侧相对的第二侧，与第一行相邻的第三侧和与第三侧相对的第四侧。每个存储单元连接到位线，高电压源和低电压源。基本上与存储单元基本相同的参考单元被均匀间隔地嵌入阵列中。高压解码器位于第一侧，连接到同一行的存储单元和参考单元。低压行解码器位于第二侧，连接到同一行中的存储单元和参考单元。感测放大器位于第三侧，连接到存储单元和参考单元。

98. 发明申请

US20110255346A1 SUB VOLT FLASH MEMORY SYSTEM 有权
标题翻译：子电压闪存系统
公开(公告)号：US20110255346A1
公开(公告)日：2011-10-20
申请号：US13172599
申请日：2011-06-29
申请人： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
发明人： Hieu Van Tran , Sang T. Nguyen , Anh Ly , Hung Q. Nguyen
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/28 , G11C16/08 , G11C16/30
摘要： Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.
摘要翻译：各种电路包括具有用于接收不同于电源电压和接地的体电压的体电压端子的MOS晶体管。可以选择性地设置体电压，使得一些MOS晶体管具有设置为电源电压或地的体电压，并且其它MOS晶体管具有不同的体电压。体电压可以被设置为MOS晶体管中的正向或反向偏置pn结。各种电路包括比较器，运算放大器，感测电路，解码电路和其它电路。电路可以包括在存储器系统中。

99. 发明授权

US08020055B2 Method and apparatus for testing the connectivity of a flash memory chip 有权
标题翻译：用于测试闪存芯片连接性的方法和装置
公开(公告)号：US08020055B2
公开(公告)日：2011-09-13
申请号：US12629302
申请日：2009-12-02
申请人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
发明人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
摘要翻译：在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。该测试电路电连接到IC的接合焊盘。在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。本发明还包括其中闪存芯片的引脚和/或存储单元被顺序发送一系列数据以测试IC的部分连通性的方法。然后检索顺序发送的数据并将其与原始数据进行比较。因此，这些数据集之间的差异突出了IC中的连接问题。

100. 发明申请

US20110080790A1 Array Of Non-volatile Memory Cells Including Embedded Local And Global Reference Cells And System 有权
标题翻译：包括嵌入式本地和全局参考单元和系统的非易失性存储单元阵列
公开(公告)号：US20110080790A1
公开(公告)日：2011-04-07
申请号：US12965504
申请日：2010-12-10
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.
摘要翻译：存储单元阵列具有与第一列相邻的第一侧，与第一侧相对的第二侧，与第一行相邻的第三侧和与第三侧相对的第四侧。每个存储单元连接到位线，高电压源和低电压源。基本上与存储单元基本相同的参考单元被均匀间隔地嵌入阵列中。高压解码器位于第一侧，连接到同一行的存储单元和参考单元。低压行解码器位于第二侧，连接到同一行中的存储单元和参考单元。感测放大器位于第三侧，连接到存储单元和参考单元。

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