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91. 发明授权

US08705282B2 Mixed voltage non-volatile memory integrated circuit with power saving 有权
标题翻译：混合电压非易失性存储器集成电路，省电
公开(公告)号：US08705282B2
公开(公告)日：2014-04-22
申请号：US13286969
申请日：2011-11-01
申请人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/30 , G11C5/147 , G11C11/5628 , G11C16/08
摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.
摘要翻译：集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。第二电压小于第一电压。可在第一电压下操作的第一电路在集成电路管芯中。可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。检测来自第二管芯焊盘的电流的电路在集成电路管芯中。开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

92. 发明申请

US20140094011A1 Self-Aligned Method Of Forming A Semiconductor Memory Array Of Floating Gate Memory Cells With Single Poly Layer 有权
标题翻译：形成具有单个多层的浮动门存储器单元的半导体存储器阵列的自对准方法
公开(公告)号：US20140094011A1
公开(公告)日：2014-04-03
申请号：US13631474
申请日：2012-09-28
申请人： Nhan Do , Vipin Tiwari , Hieu Van Tran , Xian Liu
发明人： Nhan Do , Vipin Tiwari , Hieu Van Tran , Xian Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/0847 , H01L29/42324 , H01L29/66825
摘要： A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material.
摘要翻译：一种形成半导体存储单元的方法，包括从同一多晶层形成浮置和控制栅极。在衬底上形成绝缘层，导电和第二绝缘材料层。在第二绝缘材料中形成沟槽，其向下延伸并暴露导电层。间隔件形成在沟槽中，由沟槽底部的小的和限定的间隙分开，露出导电层的一部分。然后通过穿过间隙进行各向异性蚀刻，通过导电层的暴露部分形成沟槽。沟槽填充有第三绝缘材料。去除导电层的选定部分，留下两个由第三绝缘材料隔开的块。

93. 发明申请

US20130242672A1 Non-volatile Memory Device And A Method Of Operating Same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US20130242672A1
公开(公告)日：2013-09-19
申请号：US13419269
申请日：2012-03-13
申请人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
发明人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0425 , G11C16/06 , G11C16/12 , G11C16/30 , G11C16/3418
摘要： An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.
摘要翻译：在第一导电类型的半导体衬底中的非易失性存储单元阵列。每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域，其间具有沟道区域。字线重叠在通道区域的一部分上，与第一区域相邻，并且与第一区域几乎没有或没有重叠。浮动栅极覆盖沟道区域的另一部分，并且与第一部分和第二区域相邻。耦合栅极覆盖浮栅。擦除门覆盖第二区域。位线连接到第一区域。负电荷泵电路产生负电压。控制电路响应于接收到命令信号而产生多个控制信号，并将负电压施加到未选择存储单元的字线。

94. 发明申请

US20130126958A1 Array Of Split Gate Non-volatile Floating Gate Memory Cells Having Improved Strapping Of The Coupling Gates 有权
标题翻译：阵列的分离门非易失性浮动门存储单元改进了耦合门的捆扎
公开(公告)号：US20130126958A1
公开(公告)日：2013-05-23
申请号：US13299320
申请日：2011-11-17
申请人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
发明人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.
摘要翻译：具有在行方向上延伸的具有间隔开的第一区域和在列方向上延伸的第二区域的非易失性存储器单元的阵列，其中限定在每个第二区域与其相关联的第一区域之间的通道区域。每个在行方向上延伸并定位在通道区域的第一部分上方的多个间隔开的字线门。多个间隔开的浮动栅极位于沟道区域的第二部分上方。多个间隔开的耦合栅极，每个在行方向和浮动栅极上延伸。多个间隔开的金属捆绑线，各自在行方向上延伸并且覆盖耦合门。多个间隔开的擦除栅极，每个沿行方向延伸并定位在第一区域上并且与浮栅和耦合栅极相邻。

95. 发明授权

US08339187B2 Charge pump systems and methods 有权
公开(公告)号：US08339187B2
公开(公告)日：2012-12-25
申请号：US13070405
申请日：2011-03-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： H02M3/18 , G05F3/20
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

96. 发明授权

US08018773B2 Array of non-volatile memory cells including embedded local and global reference cells and system 有权
公开(公告)号：US08018773B2
公开(公告)日：2011-09-13
申请号：US12398155
申请日：2009-03-04
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.

97. 发明授权

US07969239B2 Charge pump circuit and a novel capacitor for a memory integrated circuit 有权
标题翻译：电荷泵电路和用于存储器集成电路的新型电容器
公开(公告)号：US07969239B2
公开(公告)日：2011-06-28
申请号：US12569832
申请日：2009-09-29
申请人： Hieu Van Tran , Hung Q. Nguyen , Thuan T. Vu , Anh Ly
发明人： Hieu Van Tran , Hung Q. Nguyen , Thuan T. Vu , Anh Ly
IPC分类号： H01L25/00
CPC分类号： H02M3/07 , G11C5/145
摘要： A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed. A charge pump circuit using the foregoing described capacitor has a plurality of transistors for charging the capacitor and discharging the capacitor thereby increasing the voltage of the charge pump circuit.
摘要翻译：用于电荷泵电路的新型电容器具有具有平坦表面的基板。第一电极处于与平面间隔开的第一平面中。第二电极与第一平面中的第一电极相邻并且与第一电极间隔开并且与其电容耦合。第三电极处于与第一平面间隔开的第二平面中并与第一电极电容耦合。第四电极在第二平面中与第三电极相邻并间隔开，并且电容耦合到第三电极并电容耦合到第二电极。第一和第四电极电连接在一起，第二和第三电极电连接在一起。另外，公开了圆柱形电极和长壁电极以及电荷泵电容器逐图案填充。使用上述电容器的电荷泵电路具有多个用于对电容器充电并对电容器进行放电的晶体管，从而增加电荷泵电路的电压。

98. 发明申请

US20100188900A1 ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS 有权
标题翻译：非易失性记忆细胞的阵列和位点
公开(公告)号：US20100188900A1
公开(公告)日：2010-07-29
申请号：US12362106
申请日：2009-01-29
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0408
摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.
摘要翻译：一组非易失性存储单元被布置成多个行和列，其中每个存储单元具有至少三个端子：用于从存储单元读出信号的第一端子，高电压的第二端子在一定操作期间提供，并且在所有操作中提供低电压的第三端子。同一列中的单元具有连接到同一列中的存储器单元的第一端的公共位线。阵列包括在同一行中彼此相邻布置的存储单元的第一和第二子阵列。第一解码器位于与第一子阵列相同的行中的第一子阵列的一侧。第二解码器被定位在与第二子阵列相同的行中的第二子阵列的另一侧。第一高压线路连接到第二解码器，并且仅连接到第一子阵列中的同一行中的存储器单元的第二端子。与第一高压线不同的第二高压线路连接到第二解码器，并且仅连接到第二子阵列中同一行中的存储器单元的第二端子。低电压线连接到第一解码器和第一和第二子阵列的同一行中的存储器单元的第三端子。

99. 发明申请

US20100002509A1 INTEGRATED FLASH MEMORY SYSTEMS AND METHODS FOR LOAD COMPENSATION 有权
标题翻译：集成闪存存储器系统和负载补偿方法
公开(公告)号：US20100002509A1
公开(公告)日：2010-01-07
申请号：US12558285
申请日：2009-09-11
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/04 , G11C16/06 , G11C7/02
CPC分类号： G11C16/26
摘要： Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
摘要翻译：公开了系统和方法，其包括补偿存储器阵列中使用的电源电压的幅度变化的特征。根据一些方面，补偿电路可以为数据列提供可调谐的限流负载，其中可以调整负载来动态补偿电源电压的变化。在某些方面，补偿电路可以采用配置为电压跟随器的运算放大器。电压跟随器补偿电源电压的任何变化，迫使负载元件上的恒定电压降，从而保持恒定的负载。还可以包括其他电路，例如预充电电路，钳位电路，缓冲电路，微调电路，以及感测体效应的读出放大器电路。片上系统集成系统方面可以包括微控制器，混合IP和闪存系统，其具有彼此接口和互操作以进行负载补偿的功能和块。

100. 发明申请

US20090323415A1 FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL 有权
标题翻译：闪存存储器阵列系统，包括顶盖存储器单元
公开(公告)号：US20090323415A1
公开(公告)日：2009-12-31
申请号：US12507783
申请日：2009-07-22
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

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