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91. 发明申请

US20130264688A1 METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT SYSTEM WITH INTERCONNECTED STACKED DEVICE WAFERS 审中-公开
标题翻译：提供具有互连堆叠器件波形的集成电路系统的方法和装置
公开(公告)号：US20130264688A1
公开(公告)日：2013-10-10
申请号：US13441627
申请日：2012-04-06
申请人： Yin Qian , Hsin-Chih Tai , Duli Mao , Tiejun Dai , Howard E. Rhodes , Hongli Yang
发明人： Yin Qian , Hsin-Chih Tai , Duli Mao , Tiejun Dai , Howard E. Rhodes , Hongli Yang
IPC分类号： H01L29/06 , H01L21/28
CPC分类号： H01L24/80 , H01L21/76898 , H01L23/481 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/14634 , H01L2224/04042 , H01L2224/05567 , H01L2224/05571 , H01L2224/08145 , H01L2224/2401 , H01L2224/24105 , H01L2224/24147 , H01L2224/48151 , H01L2224/73251 , H01L2224/80357 , H01L2224/80896 , H01L2224/80986 , H01L2224/82031 , H01L2224/82106 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/3511 , H01L2224/80001 , H01L2924/00012 , H01L2224/05552
摘要： An integrated circuit system includes a first device wafer that has a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer that has a second semiconductor layer proximate to a second metal layer including a second conductor disposed within a second metal layer oxide is also included. A frontside of the first metal layer oxide is bonded to a frontside of the second metal layer oxide at an oxide bonding interface between the first metal layer oxide and the second metal layer oxide. A conductive path couples the first conductor to the second conductor with conductive material formed in a cavity etched between the first conductor and the second conductor and etched through the oxide bonding interface and through the second semiconductor layer from a backside of the second device wafer.
摘要翻译：集成电路系统包括具有靠近第一金属层的第一半导体层的第一器件晶片，第一金属层包括设置在第一金属层氧化物内的第一导体。还包括具有靠近第二金属层的第二半导体层的第二器件晶片，该第二金属层包括设置在第二金属层氧化物内的第二导体。在第一金属层氧化物和第二金属层氧化物之间的氧化物接合界面处，第一金属层氧化物的前侧结合到第二金属层氧化物的前侧。导电路径将第一导体耦合到第二导体，导电材料形成在蚀刻在第一导体和第二导体之间的空腔中，并通过氧化物接合界面从第二器件晶片的背面蚀刻穿过第二半导体层。

92. 发明申请

US20130082163A1 IMAGE SENSOR WITH MICRO-LENS COATING 有权
标题翻译：具有微透镜涂层的图像传感器
公开(公告)号：US20130082163A1
公开(公告)日：2013-04-04
申请号：US13252883
申请日：2011-10-04
申请人： Gang Chen , Hsin-Chih Tai , Duli Mao , Howard E. Rhodes
发明人： Gang Chen , Hsin-Chih Tai , Duli Mao , Howard E. Rhodes
IPC分类号： H01L27/148 , B23P25/00
CPC分类号： H01L27/14627 , H01L27/14685 , Y10T29/49885
摘要： Techniques and architectures for providing a coating for one or more micro-lenses of a pixel array. In an embodiment, a pixel element includes a micro-lens and a coating portion extending over a surface of the micro-lens, where a profile of the coating portion is super-conformal to, or at least conformal to, a profile of the micro-lens. In another embodiment, the coating portion is formed at least in part by orienting the surface of the micro-lens to face generally downward with the direction of gravity, the orienting to allow a fluid coating material to flow for formation of the coating portion.
摘要翻译：用于为像素阵列的一个或多个微透镜提供涂层的技术和架构。在一个实施例中，像素元件包括微透镜和在微透镜的表面上延伸的涂层部分，其中涂层部分的轮廓与微观透镜的轮廓超共形或至少共形 -镜片。在另一个实施例中，涂覆部分至少部分地通过使微透镜的表面定向以与重力方向大致向下的方式形成，定向以允许流体涂覆材料流动以形成涂覆部分。

93. 发明申请

US20130258144A1 SYSTEM, APPARATUS AND METHOD FOR DARK CURRENT CORRECTION 审中-公开
标题翻译：用于暗电流校正的系统，装置和方法
公开(公告)号：US20130258144A1
公开(公告)日：2013-10-03
申请号：US13432958
申请日：2012-03-28
申请人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
发明人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
IPC分类号： H04N9/64
CPC分类号： H01L27/14623 , H01L27/14627 , H01L27/1464
摘要： Embodiments of the invention describe a system, apparatus and method for obtaining black reference pixels for dark current correction processing are described herein. Embodiments of the invention capture image signal data via a plurality of pixel cells of a pixel unit of an image device, wherein capturing image signal data involves establishing a first state of exposing incident light on each pixel of the pixel unit and a second state of shielding incident light from one or more pixels of the pixel unit via a shutter unit disposed over the pixel unit. Image signal data from each pixel of the pixel unit captured during the first state and the second state is read, and scene image data is created by combining a subset of image signal data captured during the first state with a dark current component including a subset of image signal data captured during the second state.
摘要翻译：本发明的实施例描述了用于获得用于暗电流校正处理的黑色参考像素的系统，装置和方法。本发明的实施例经由图像装置的像素单元的多个像素单元捕获图像信号数据，其中捕获图像信号数据涉及建立在像素单元的每个像素上曝光入射光的第一状态和第二屏蔽状态通过设置在像素单元上的快门单元，来自像素单元的一个或多个像素的入射光。读取在第一状态和第二状态期间捕获的像素单元的每个像素的图像信号数据，并且通过将在第一状态期间捕获的图像信号数据的子集与包括一个在第二状态期间捕获的图像信号数据。

94. 发明授权

US08933544B2 Integrated circuit stack with integrated electromagnetic interference shielding 有权
标题翻译：具有集成电磁干扰屏蔽的集成电路堆栈
公开(公告)号：US08933544B2
公开(公告)日：2015-01-13
申请号：US13547997
申请日：2012-07-12
申请人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
发明人： Duli Mao , Hsin-Chih Tai , Yin Qian , Tiejun Dai , Howard E. Rhodes , Hongli Yang
IPC分类号： H01L23/552 , H01L27/146
CPC分类号： H01L27/14623 , H01L27/14634 , H01L27/1464 , H01L27/1469
摘要： An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.
摘要翻译：集成电路系统包括具有靠近第一金属层的第一半导体层的第一器件晶片，第一金属层包括设置在第一金属层氧化物内的第一导体。具有靠近包括第二导体的第二金属层的第二半导体层的第二器件晶片设置在第二金属层氧化物内。第一器件晶片的前端在接合界面处结合到第二器件晶片的前侧。导电路径通过接合界面将第一导体耦合到第二导体。第一金属EMI屏蔽设置在第一金属氧化物层和第二金属层氧化物层之一中。第一EMI屏蔽包括在最靠近接合界面的第一金属氧化物层和第二金属层氧化物层中的所述一个的金属层中。

95. 发明申请

US20130217173A1 METHODS OF FORMING VARYING DEPTH TRENCHES IN SEMICONDUCTOR DEVICES 有权
标题翻译：在半导体器件中形成变化深度的方法
公开(公告)号：US20130217173A1
公开(公告)日：2013-08-22
申请号：US13402674
申请日：2012-02-22
申请人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
发明人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
IPC分类号： H01L31/02
CPC分类号： H01L21/76229 , H01L27/1463 , H01L27/14689
摘要： A method of forming trenches in a semiconductor device includes forming an etchant barrier layer above a first portion of a semiconductor layer. A first trench is etched in a second portion of the semiconductor layer using a first etchant. The second portion of the semiconductor layer is not disposed underneath the etchant barrier layer. The etchant barrier layer is etched through using a second etchant that does not substantially etch the semiconductor layer. A second trench is etched in the first portion of the semiconductor layer using a third etchant. The third etchant also extends a depth of the first trench.
摘要翻译：在半导体器件中形成沟槽的方法包括在半导体层的第一部分上方形成蚀刻剂阻挡层。使用第一蚀刻剂在半导体层的第二部分中蚀刻第一沟槽。半导体层的第二部分不设置在蚀刻剂阻挡层下方。通过使用不基本上蚀刻半导体层的第二蚀刻剂蚀刻蚀刻剂阻挡层。使用第三蚀刻剂在半导体层的第一部分中蚀刻第二沟槽。第三蚀刻剂还延伸第一沟槽的深度。

96. 发明申请

US20130069188A1 DUAL-FACING CAMERA ASSEMBLY 有权
公开(公告)号：US20130069188A1
公开(公告)日：2013-03-21
申请号：US13235121
申请日：2011-09-16
申请人： Gang Chen , Ashish Shah , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
发明人： Gang Chen , Ashish Shah , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
IPC分类号： H01L31/0232 , H01L31/02
CPC分类号： H01L27/14645 , H01L27/14605 , H01L27/1462 , H01L27/14621 , H01L27/14627 , H01L27/14634 , H01L27/14636 , H01L27/1464 , H01L27/1469
摘要： Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate).In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.

97. 发明申请

US20120313197A1 IN-PIXEL HIGH DYNAMIC RANGE IMAGING 有权
标题翻译：内像素高动态范围成像
公开(公告)号：US20120313197A1
公开(公告)日：2012-12-13
申请号：US13155969
申请日：2011-06-08
申请人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
发明人： Gang Chen , Duli Mao , Hsin-Chih Tai , Howard E. Rhodes
IPC分类号： H01L27/146
CPC分类号： H01L27/14616 , H01L27/14612 , H01L27/14643
摘要： Embodiments of the invention describe providing high dynamic range imaging (HDRI or simply HDR) to an imaging pixel by coupling a floating diffusion node of the imaging pixel to a plurality of metal-oxide semiconductor (MOS) capacitance regions. It is understood that a MOS capacitance region only turns “on” (i.e., changes the overall capacitance of the floating diffusion node) when the voltage at the floating diffusion node (or a voltage difference between a gate node and the floating diffusion node) is greater than its threshold voltage; before the MOS capacitance region is “on” it does not contribute to the overall capacitance or conversion gain of the floating diffusion node.Each of the MOS capacitance regions will have different threshold voltages, thereby turning “on” at different illumination conditions. This increases the dynamic range of the imaging pixel, thereby providing HDR for the host imaging system.
摘要翻译：本发明的实施例描述了通过将成像像素的浮动扩散节点耦合到多个金属氧化物半导体（MOS）电容区域来向成像像素提供高动态范围成像（HDRI或简单的HDR）。应当理解，当浮动扩散节点处的电压（或者栅极节点和浮动扩散节点之间的电压差）大于MOS晶体管时，MOS电容区域仅导通（即，改变浮动扩散节点的总体电容）其阈值电压; 在MOS电容区域之前，它不会对浮动扩散节点的整体电容或转换增益有贡献。每个MOS电容区域将具有不同的阈值电压，从而在不同的照明条件下导通。这增加了成像像素的动态范围，从而为主机成像系统提供HDR。

98. 发明授权

US08097890B2 Image sensor with micro-lenses of varying focal lengths 有权
标题翻译：具有不同焦距的微透镜的图像传感器
公开(公告)号：US08097890B2
公开(公告)日：2012-01-17
申请号：US12029400
申请日：2008-02-11
申请人： WeiDong Qian , Hsin-Chih Tai , Vincent Venezia , Howard E. Rhodes
发明人： WeiDong Qian , Hsin-Chih Tai , Vincent Venezia , Howard E. Rhodes
IPC分类号： H01L33/00
CPC分类号： G02B3/0018 , H01L27/14627
摘要： An image sensor having a plurality of micro-lenses disposed on a semiconductor substrate. A first micro-lens has a different focal length, height, shape, curvature, thickness, etc., than a second micro-lens. The image sensor may be back side illuminated or front side illuminated.
摘要翻译：一种具有设置在半导体衬底上的多个微透镜的图像传感器。第一微透镜具有与第二微透镜不同的焦距，高度，形状，曲率，厚度等。图像传感器可以是背面照明的或正面照亮的。

99. 发明申请

US20090200623A1 IMAGE SENSOR WITH MICRO-LENSES OF VARYING FOCAL LENGTHS 有权
标题翻译：具有变化关键长度的微镜的图像传感器
公开(公告)号：US20090200623A1
公开(公告)日：2009-08-13
申请号：US12029400
申请日：2008-02-11
申请人： WeiDong Qian , Hsin-Chih Tai , Vincent Venezia , Howard E. Rhodes
发明人： WeiDong Qian , Hsin-Chih Tai , Vincent Venezia , Howard E. Rhodes
IPC分类号： H01L31/0232 , G02B27/12
CPC分类号： G02B3/0018 , H01L27/14627
摘要： An image sensor having a plurality of micro-lenses disposed on a semiconductor substrate. A first micro-lens has a different focal length, height, shape, curvature, thickness, etc., than a second micro-lens. The image sensor may be back side illuminated or front side illuminated.
摘要翻译：一种具有设置在半导体衬底上的多个微透镜的图像传感器。第一微透镜具有与第二微透镜不同的焦距，高度，形状，曲率，厚度等。图像传感器可以是背面照明的或正面照亮的。

100. 发明申请

US20130113969A1 METHOD, APPARATUS AND SYSTEM FOR PROVIDING IMPROVED FULL WELL CAPACITY IN AN IMAGE SENSOR PIXEL 有权
标题翻译：在图像传感器像素中提供改善的全能力的方法，装置和系统
公开(公告)号：US20130113969A1
公开(公告)日：2013-05-09
申请号：US13288880
申请日：2011-11-03
申请人： Sohei Manabe , Keh-Chiang Ku , Vincent Venezia , Hsi-Chih Tai , Duli Mao , Howard E. Rhodes
发明人： Sohei Manabe , Keh-Chiang Ku , Vincent Venezia , Hsi-Chih Tai , Duli Mao , Howard E. Rhodes
IPC分类号： H04N5/335
CPC分类号： H01L27/14643 , H01L27/1461 , H01L27/14612 , H01L27/14616 , H01L27/1463 , H01L27/14641
摘要： Techniques and mechanisms for improving full well capacity for pixel structures in an image sensor. In an embodiment, a first pixel structure of the image sensor includes an implant region, where a skew of the implant region corresponds to an implant angle, and a second pixel structure of the image sensor includes a transfer gate. In another embodiment, an offset of the implant region of the first pixel structure from the transfer gate of the second pixel structure corresponds to the implant angle.
摘要翻译：用于提高图像传感器中像素结构的完整容量的技术和机制。在一个实施例中，图像传感器的第一像素结构包括植入区域，其中植入区域的偏斜对应于植入角度，并且图像传感器的第二像素结构包括传输门。在另一个实施例中，第一像素结构的注入区域与第二像素结构的传输门的偏移对应于植入角度。

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