会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 99. 发明授权
    • Residue circuit
    • 残留电路
    • US5499202A
    • 1996-03-12
    • US253057
    • 1994-06-02
    • Tsugio TakahashiHitoshi FujitaHiroshi Okamoto
    • Tsugio TakahashiHitoshi FujitaHiroshi Okamoto
    • G06F7/496G06F7/72G06F7/52G06F7/50
    • G06F7/727
    • A residue circuit takes weights of even number bits of a dividend as 1 and weights of odd number bits of the dividend as 2. The circuit includes a plurality of adders for summing bits having weight 1 to output weight 1 at a summing output and weight 2 at a carry output, and a plurality of adders for summing bits having weight 2 to output weight 2 at a summing output and weight 1 at a carry output. With these adders, summing of respective bits of the dividend bits are performed taking the weights into account to repeat summing until the number of bits finally becomes 3 bits. Depending upon the pattern of this 3 bits, a remainder is output by a modulus 3 generation circuit.
    • 残余电路将除数的偶数位的权重设为1,并且将被除数的奇数位的权重作为2.该电路包括多个加法器,用于将加权1的位相加以在加法输出和权重2处输出权重1 以及多个加法器,用于对具有权重2的位进行求和,以在加法输出处输出权重2,并在进位输出处加权1。 利用这些加法器,对于重复求和,考虑权重来执行除数比特的各个比特的相加,直到比特数最终变为3比特。 根据该3位的模式,余数由模数3生成电路输出。