专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20090239348A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090239348A1
公开(公告)日：2009-09-24
申请号：US12478345
申请日：2009-06-04
申请人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
发明人： Sun-Ghil Lee , Young-Pil Kim , Yu-Gyun Shin , Jong-Wook Lee , Young-Eun Lee
IPC分类号： H01L21/336
CPC分类号： C30B29/06 , C30B15/00
摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
摘要翻译：公开了一种形成在应变硅层上的半导体器件及其制造方法。根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

92. 发明授权

US07553742B2 Method(s) of forming a thin layer 有权
标题翻译：形成薄层的方法
公开(公告)号：US07553742B2
公开(公告)日：2009-06-30
申请号：US11329158
申请日：2006-01-11
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/76
CPC分类号： C30B25/04 , C30B29/06 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.
摘要翻译：一种形成薄层的方法，包括提供通过绝缘图案中的开口局部暴露的第一单晶硅层，并在第一单晶硅层上形成外延层，并在绝缘图案上形成非晶硅层，非晶硅层，其具有与外延层相邻的第一部分和与第一部分间隔开的第二部分，其中非晶硅层在第一部分和第二部分以基本上相同的速率形成在绝缘图案上。可以将非晶硅层形成为均匀的厚度而没有变薄的缺陷。

93. 发明授权

US07351622B2 Methods of forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US07351622B2
公开(公告)日：2008-04-01
申请号：US11490613
申请日：2006-07-21
申请人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
发明人： Gyoung-Ho Buh , Chang-Woo Ryoo , Yu-Gyun Shin , Tai-Su Park , Jin-Wook Lee
IPC分类号： H01L21/84 , H01L21/8234 , H01L21/336 , H01L21/00
CPC分类号： H01L29/7851 , H01L29/42392 , H01L29/66795 , H01L29/66803
摘要： A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成由半导体形成的三维结构，并且通过使用第一源气体和第二源气体进行等离子体掺杂工艺，对三维结构进行各向同性地掺杂。第一源气体包括n型或p型杂质元素，第二源气体包括稀释元件，而与掺杂区域的电特性无关。

94. 发明申请

US20070057292A1 SONOS type non-volatile semiconductor devices and methods of forming the same 审中-公开
标题翻译： SONOS型非易失性半导体器件及其形成方法
公开(公告)号：US20070057292A1
公开(公告)日：2007-03-15
申请号：US11518656
申请日：2006-09-11
申请人： Hong-Bae Park , Yu-Gyun Shin
发明人： Hong-Bae Park , Yu-Gyun Shin
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L29/40117
摘要： A SONOS type non-volatile semiconductor device includes a semiconductor substrate, source/drain regions doped with impurities formed in the semiconductor substrate, a channel region formed in the semiconductor substrate between the source/drain regions, a tunnel insulation layer formed on the channel region, a charge-trapping layer formed on the tunnel insulation layer, a blocking insulation layer formed on the charge-trapping layer, and a gate electrode formed on the blocking insulation layer. The charge-trapping layer includes aluminum nitride having a chemical formula AlxNy and/or the blocking insulation layer includes aluminum nitride having a chemical formula AlpNq, such that x, y, p, and q are positive integers, x and y satisfy a relation x>y, and p and q satisfy a relation p
摘要翻译： SONOS型非易失性半导体器件包括半导体衬底，掺杂在半导体衬底中形成的杂质的源/漏区，形成在源/漏区之间的半导体衬底中的沟道区，形成在沟道区上的隧道绝缘层形成在隧道绝缘层上的电荷俘获层，形成在电荷俘获层上的阻挡绝缘层，以及形成在阻挡绝缘层上的栅电极。电荷捕获层包括具有化学式Al x N y Y的氮化铝和/或阻挡绝缘层包括具有化学式为Al < x，y，p和q是正整数，x和y满足关系x> y，p和q满足关系p

95. 发明申请

US20060145254A1 Semiconductor devices including carrier accumulation layers and methods for fabricating the same 失效
标题翻译：包括载体积聚层的半导体器件及其制造方法
公开(公告)号：US20060145254A1
公开(公告)日：2006-07-06
申请号：US11322335
申请日：2005-12-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L21/28247 , H01L21/28273 , H01L21/28282 , H01L29/6659 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.
摘要翻译：半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。表面绝缘层与源极/漏极区之间的界面包括多个界面状态。紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。载体积聚层沿着间隔物下的界面延伸。还讨论了相关方法。

96. 发明申请

US20050277235A1 Methods of manufacturing semiconductor devices having single crystalline silicon layers and related semiconductor devices 有权
标题翻译：制造具有单晶硅层和相关半导体器件的半导体器件的方法
公开(公告)号：US20050277235A1
公开(公告)日：2005-12-15
申请号：US11121562
申请日：2005-05-04
申请人： Yong-Hoon Son , Yu-Gyun Shin
发明人： Yong-Hoon Son , Yu-Gyun Shin
IPC分类号： C30B1/00 , C30B3/00 , C30B5/00 , C30B28/02 , H01L21/00 , H01L21/20 , H01L21/30 , H01L21/36 , H01L21/46 , H01L21/822 , H01L21/84 , H01L27/06
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/8221 , H01L27/0688
摘要： Methods of manufacturing semiconductor devices having at least one single crystal silicon layer are provided. Pursuant to these methods, a first seed layer that includes silicon is formed. A first non-single crystalline silicon layer is then formed on the first seed layer. The first non-single crystalline silicon layer is irradiated with a laser to transform the first non-single crystalline silicon layer into a first single crystalline silicon layer. Corresponding semiconductor devices are also disclosed.
摘要翻译：提供具有至少一个单晶硅层的半导体器件的制造方法。根据这些方法，形成包括硅的第一籽晶层。然后在第一种子层上形成第一非单晶硅层。用激光照射第一非单晶硅层，以将第一非单晶硅层转变为第一单晶硅层。还公开了相应的半导体器件。

97. 发明授权

US08691649B2 Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices 有权
标题翻译：形成凹槽阵列晶体管的方法和制造半导体器件的方法
公开(公告)号：US08691649B2
公开(公告)日：2014-04-08
申请号：US13151494
申请日：2011-06-02
申请人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
摘要翻译：在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。可以在栅极氧化物层上形成栅电极以填充凹部。源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。因此，氧化物层可以具有均匀的厚度分布和致密结构。

98. 发明申请

US20100197089A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH METAL-SEMICONDUCTOR COMPOUND SOURCE/DRAIN CONTACT REGIONS 审中-公开
标题翻译：用金属半导体复合源/漏极接触区制造半导体器件的方法
公开(公告)号：US20100197089A1
公开(公告)日：2010-08-05
申请号：US12699491
申请日：2010-02-03
申请人： Jin-Bum Kim , Yu-Gyun Shin , Jung-Yun Won , In-Sun Jung , Jun-Ho Lee
发明人： Jin-Bum Kim , Yu-Gyun Shin , Jung-Yun Won , In-Sun Jung , Jun-Ho Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/28518 , H01L21/28525 , H01L21/2855 , H01L21/32053 , H01L21/76814 , H01L21/76838 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L21/823871 , H01L23/53238 , H01L23/53266 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor devices include forming a transistor on and/or in a semiconductor substrate, wherein the transistor includes a source/drain region and a gate pattern disposed on a channel region adjacent the source/drain region. An insulating layer is formed on the transistor and patterned to expose the source/drain region. A semiconductor source layer is formed on the exposed source/drain region and on an adjacent portion of the insulating layer. A metal source layer is formed on the semiconductor source layer. Annealing, is performed to form a first metal-semiconductor compound region on the source/drain region and a second metal-semiconductor compound region on the adjacent portion of the insulating layer. The first metal-semiconductor compound region may be thicker than the second metal-semiconductor compound region. The metal source layer may include a metal layer and a metal nitride barrier layer.
摘要翻译：制造半导体器件的方法包括在半导体衬底上和/或半导体衬底中形成晶体管，其中晶体管包括源极/漏极区域和设置在与源极/漏极区域相邻的沟道区域上的栅极图案。在晶体管上形成绝缘层并图案化以暴露源/漏区域。在暴露的源极/漏极区域和绝缘层的相邻部分上形成半导体源极层。在半导体源层上形成金属源层。进行退火以在源极/漏极区域上形成第一金属 - 半导体化合物区域和在绝缘层的相邻部分上形成第二金属 - 半导体化合物区域。第一金属 - 半导体化合物区域可以比第二金属 - 半导体化合物区域厚。金属源层可以包括金属层和金属氮化物阻挡层。

99. 发明授权

US07652340B2 Fin field effect transistor and method of manufacturing the same 有权
标题翻译： Fin场效应晶体管及其制造方法
公开(公告)号：US07652340B2
公开(公告)日：2010-01-26
申请号：US11952676
申请日：2007-12-07
申请人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
发明人： Deok-Hyung Lee , Yu-Gyun Shin , Jong-Wook Lee , Min-Gu Kang
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795 , H01L29/7854
摘要： In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern. Internal stresses that can be generated in sidewalls of the active pattern are sufficiently released and an original shape of the first silicon nitride pattern remains unchanged, thereby improving electrical characteristics of the fin FET.
摘要翻译：在鳍状场效应晶体管（FET）中，有源图案在垂直方向上从基板突出，并且在第一水平方向上延伸穿过基板。第一氮化硅图案形成在有源图案上，并且第一氧化物图案和第二氮化硅图案依次形成在衬底上和活性图案的下部的侧壁上。在第二氮化硅图案上形成器件隔离层，器件隔离层的顶表面与氧化物图案和第二氮化硅图案的顶表面共面。在第一氧化物图案和第二氮化硅图案之间形成具有相对于第二氮化硅图案的蚀刻选择性的缓冲图案。可以在有源图案的侧壁中产生的内部应力被充分地释放，并且第一氮化硅图案的原始形状保持不变，从而改善了鳍式FET的电特性。

100. 发明授权

US07537980B2 Method of manufacturing a stacked semiconductor device 有权
标题翻译：叠层半导体器件的制造方法
公开(公告)号：US07537980B2
公开(公告)日：2009-05-26
申请号：US11510622
申请日：2006-08-28
申请人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
发明人： Yong-Hoon Son , Yu-Gyun Shin , Jong-Wook Lee
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/336 , H01L29/94 , C30B33/06
CPC分类号： H01L21/76879 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02675 , H01L21/28525 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L23/535 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially filling the first opening. A second SEG process may be performed to form a second plug filling the first opening. A third SEG process may be carried out to form a first channel layer on the first insulation interlayer pattern. A second insulation interlayer may be formed on the first channel layer. The second insulation interlayer, the first channel layer and the second plug arranged on the first plug may be removed to expose the first plug. The first plug may be removed to form a serial opening. The serial opening may be filled with a metal wiring.
摘要翻译：在制造叠层半导体器件的方法中，可以制备包括杂质区的晶种层。可以在种子层上形成具有第一开口的第一绝缘层间图案。可以执行第一SEG过程以形成部分填充第一开口的第一插塞。可以执行第二SEG过程以形成填充第一开口的第二塞子。可以执行第三SEG处理以在第一绝缘夹层图案上形成第一沟道层。可以在第一沟道层上形成第二绝缘中间层。布置在第一插头上的第二绝缘中间层，第一沟道层和第二插塞可以被去除以暴露第一插塞。可以移除第一个插头以形成串行开口。串行开口可以用金属布线填充。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式