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91. 发明授权

US06922804B2 Dynamic end to end retransmit apparatus and method 失效
标题翻译：动态端对端重传设备及方法
公开(公告)号：US06922804B2
公开(公告)日：2005-07-26
申请号：US10092550
申请日：2002-03-08
申请人： Debendra Das Sharma
发明人： Debendra Das Sharma
IPC分类号： G06F11/14 , G06F13/00 , H04B1/74 , H04L1/22 , H04L1/00
CPC分类号： H04L1/22 , H04B1/74
摘要： A dynamic end to end retry apparatus and method uses the concept of transaction identification numbers combined with a path number and flow control class to uniquely account for all transactions in a multi-processor computer system. The apparatus and method ensure there are no duplicate transactions through the use of special probe and plunge transactions and their respective responses. The apparatus and method also allow for any number of alternate paths being active simultaneously, such that if one path fails, the remaining alternate paths can continue on the communication (along with the backup alternate path if desired) as usual without any loss of transactions.
摘要翻译：动态的端对端重试设备和方法使用与路径号和流控制类相结合的事务标识号的概念来唯一地说明多处理器计算机系统中的所有事务。该设备和方法通过使用特殊的探针和插入事务及其各自的响应确保没有重复的事务。该装置和方法还允许任何数量的备用路径同时被激活，使得如果一个路径失效，则如通常那样，其余备用路径可以在通信上继续（如果需要，与备用备用路径一起），而没有任何事务丢失。

92. 发明授权

US06799287B1 Method and apparatus for verifying error correcting codes 有权
标题翻译：验证纠错码的方法和装置
公开(公告)号：US06799287B1
公开(公告)日：2004-09-28
申请号：US09562133
申请日：2000-05-01
申请人： Debendra Das Sharma , Elizabeth S. Wolf
发明人： Debendra Das Sharma , Elizabeth S. Wolf
IPC分类号： G06F1110
CPC分类号： H03M13/47
摘要： A method and an apparatus verifies the correctness of the error correcting code algorithm and the correctness of the error correcting code implementation. An error injection module is used to inject random errors into an ECC circuit between an encoder and a decoder. The encoder encodes data bits with check bits to produce an encoded signal. A decoder decodes the encoded signal, after modification by the error injection module. The output of the decoder may be a zero error signal, a signal error signal, a multiple error signal, and an error location signal. The output signal is compared to expected values to determine if an error exists in the ECC or the ECC circuit.
摘要翻译：一种方法和装置验证纠错码算法的正确性和纠错码实现的正确性。使用错误注入模块将随机错误注入到编码器和解码器之间的ECC电路中。编码器用校验位对数据位进行编码，以产生编码信号。解码器通过错误注入模块修改后对编码信号进行解码。解码器的输出可以是零误差信号，信号误差信号，多误差信号和误差位置信号。将输出信号与预期值进行比较，以确定ECC或ECC电路中是否存在错误。

93. 发明授权

US06647469B1 Using read current transactions for improved performance in directory-based coherent I/O systems 有权
公开(公告)号：US06647469B1
公开(公告)日：2003-11-11
申请号：US09562191
申请日：2000-05-01
申请人： Debendra Das Sharma , Sharon M. Ebner , John A. Wickeraad , Joe P. Cowan , Carl H. Jackson
发明人： Debendra Das Sharma , Sharon M. Ebner , John A. Wickeraad , Joe P. Cowan , Carl H. Jackson
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F2212/621
摘要： A shared memory provides data access to a plurality of agents (e.g., processor, cells of processors, I/O controllers, etc.) and includes a memory and a memory controller. The memory controller selectively provides memory access to the agents in both coherent and read current modes of operation. In the coherent mode, the memory controller ensures that the data stored in system memory is accurately and precisely mirrored in all subservient copies of that data as might typically be stored in agent cache memories. Using, for example, a MESI type protocol, the memory controller limits access to memory so that only an “owner” or a particular portion or line of memory has write access and that, during the extension of these write privileges, no other agent has a valid copy of the data subject to being updated. Thus, the memory controller implements a first set of rule in the coherent mode of operation to insure that all copies of data stored by the agents are coherent with data stored in the memory. In a read current mode of access, a read-once segment of data is copied to an agent with the agent implementing a second set of rules to minimize or eliminate the possibility that the data might become stale prior to use or that it be misused by another agent or process. Thus, in the read current, an “uncontrolled” copy of the data is released subject to certain restrictions to be implemented by the receiving agent as defined by a second set of rules. For example, these rules require that the agent's copy of data be provided as an output and then invalidated within a predetermined period of time, that the agent have limit access to the memory during any set of fetch operations to no more than a predetermined maximum block size. Also included is a requirement that the copy of data include only that data contained within a range of memory addresses, the range beginning within a predetermined block of memory addresses and continuing through an end of block address. These limitations limit the amount of data that might be subject to misuse, particularly in the case of a failure resulting in the inability of a requesting agent to complete a transaction according to the rules.

94. 发明授权

US06473877B1 ECC code mechanism to detect wire stuck-at faults 失效
标题翻译： ECC代码机制，用于检测电线卡住故障
公开(公告)号：US06473877B1
公开(公告)日：2002-10-29
申请号：US09438063
申请日：1999-11-10
申请人： Debendra Das Sharma
发明人： Debendra Das Sharma
IPC分类号： H02M1300
CPC分类号： G11B20/1816 , G11B20/18
摘要： The inventive mechanism detects wire stuck-at faults, which can be used with any other ECC code. The inventive mechanism determines the number of 1's (or 0's) in the data portion and the ECC code of the data portion. This counted number is then provided with ECC code. The data portion, its ECC, the counted number, and its ECC are transmitted to the destination. At the destination, the message is decoded, and the number of 1's in the received message is compared with the counted number, if there is a discrepancy, then a wire fault is signaled. The mechanism may also detect any number of faults provided the number of 0 to 1 transitions is not the same as the number of 1 to 0 transitions. The mechanism can be reconfigured to work with any transmission wire width.
摘要翻译：本发明的机构检测线卡住故障，可以与任何其他ECC代码一起使用。本发明的机构确定数据部分中的1（或0）的数目和数据部分的ECC码。然后将该计数的数字提供ECC码。将数据部分，其ECC，计数和其ECC发送到目的地。在目的地，消息被解码，并且将接收到的消息中的1的数目与计数进行比较，如果存在差异，则发出有线故障。如果0到1个转换的数量与1到0个转换的数量不同，则该机制还可以检测任何数量的故障。该机构可以重新配置为与任何传输线宽度一起工作。

95. 发明授权

US06285686B1 Using page registers for efficient communication 失效
标题翻译：使用页面寄存器进行高效通信
公开(公告)号：US06285686B1
公开(公告)日：2001-09-04
申请号：US09044659
申请日：1998-03-19
申请人： Debendra Das Sharma
发明人： Debendra Das Sharma
IPC分类号： H04J318
CPC分类号： H04L69/04 , H04L69/22
摘要： The inventive mechanism reduces the bandwidth required to transmit an information packet. The inventive mechanism uses page registers that store the bit patterns that are likely to repeat. The information includes a reference to the stored pattern in place of the pattern. Both the receiving node and the sending node store the pattern. A sender would review its page registers to determine if the bit pattern which it is about to send is already present. If it exists, it sends the page register number instead of the bit pattern. The resultant reduction in packet length increases the usable bandwidth. If the entry does not exist in the page registers, and the bit pattern is likely to repeat in the fixed bit positions, the sender may store the bits in a particular page register and send the packet with all the bits, and include a format that tells the receiver to store the repeated bits in the same page register number where the sender stored the bits. Subsequent transactions with the same bit patterns will benefit from the page register usage.
摘要翻译：本发明的机制减少了发送信息分组所需的带宽。本发明的机制使用存储可能重复的位模式的页寄存器。信息包括对存储的图案的引用以代替图案。接收节点和发送节点都存储模式。发送者将检查其页面寄存器以确定其将要发送的位模式是否已经存在。如果存在，它发送页寄存器编号而不是位模式。由此导致的分组长度的减少增加了可用带宽。如果页面寄存器中不存在条目，并且位模式可能在固定位位置重复，则发送方可以将位存储在特定页寄存器中，并发送具有所有位的数据包，并且包括格式告知接收器将重复的位存储在发送方存储位的同一页寄存器号中。具有相同位模式的后续交易将从页面寄存器使用中受益。

96. 发明授权

US06076130A System and method for efficient communication between buses 失效
标题翻译：公交车间高效通信的系统和方法
公开(公告)号：US06076130A
公开(公告)日：2000-06-13
申请号：US44660
申请日：1998-03-19
申请人： Debendra Das Sharma
发明人： Debendra Das Sharma
IPC分类号： G06F13/36 , G06F13/40 , G06F13/38
CPC分类号： G06F13/4036
摘要： The inventive mechanism has a bypassable transaction that is directly loaded to the bypass queue. For example, all read transactions from a PCI bus are directly loaded to the bypass queue. This avoids the route through the common queue to the bypass queue for a read transaction that cannot be loaded on the second PCI bus. Two single bit wide queues are required to enforce ordering, the lock queue and the key queue. The lock queue has the same depth as the bypass queue and is affiliated to it. The key queue is affiliated to the common queue and has the same depth as the common queue. When an entry is loaded to the bypass queue, it is locked by setting the corresponding bit in the lock queue to 1 if there is at least one entry in the common queue and the previous entry was loaded into the common queue. If an incoming transaction to the bypass queue is locked in the lock queue, the entry in the key queue corresponding to the last entry in the common queue is also set to 1. Thus, for every locked entry in the bypass queue a key is set in the common queue. A locked entry cannot be unloaded until the corresponding keyed entry is unloaded.
摘要翻译：本发明的机制具有直接加载到旁路队列的可旁路事务。例如，所有从PCI总线读取的事务都直接加载到旁路队列中。这避免了通过公共队列到不能在第二个PCI总线上加载的读取事务的旁路队列的路由。需要两个单个位宽的队列来强制执行排序，锁定队列和密钥队列。锁定队列具有与旁路队列相同的深度，并与其附属。密钥队列隶属于公共队列，具有与普通队列相同的深度。当条目加载到旁路队列时，如果公共队列中至少有一个条目，并将上一个条目加载到公共队列中，则锁定队列中的相应位将被锁定为1。如果到旁路队列的进入事务被锁定在锁定队列中，则对应于公共队列中最后一个条目的密钥队列中的条目也被设置为1.因此，对于旁路队列中的每个锁定条目，设置一个密钥在共同的队列中。锁定的条目不能卸载，直到相应的密钥条目被卸载。

97. 发明授权

US5978574A Formal verification of queue flow-control through model-checking 失效
标题翻译：通过模型检查对队列流量控制进行正式验证
公开(公告)号：US5978574A
公开(公告)日：1999-11-02
申请号：US964811
申请日：1997-11-05
申请人： Debendra Das Sharma
发明人： Debendra Das Sharma
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/504
摘要： The inventive system and method for verifying flow control of a queue on a cycle by cycle basis, involves modeling the queue, checking for an overflow condition and an underflow condition in the model during each cycle, and determining any changes to the number of entries in the queue during the cycle. This mechanism is repeated until each cycle has been verified. The queue is modeled to have a number of entries in the range of -1 to N+1, where N is the maximum number of entries the queue may hold, -1 represents the underflow condition, and N+1 represents the overflow condition. To accurately represent the number of entries in each cycle, the number of entries that the each producer and each consumer is capable of adding to or subtracting from the queue in each cycle is modelled.
摘要翻译：本发明的用于逐周期验证队列的流量控制的系统和方法包括对每个周期中的队列进行建模，检查模型中的溢出条件和下溢条件，以及确定对每个周期中的条目数量的任何改变在循环中排队。重复这个机制，直到每个循环都被验证。队列被建模为具有-1到N + 1范围内的多个条目，其中N是队列可以保存的最大条目数，-1表示下溢条件，N + 1表示溢出条件。为了准确地表示每个周期中的条目数，每个生成器和每个消费者能够在每个周期中从队列中添加或减去的条目数被建模。

98. 发明授权

US10671476B2 In-band margin probing on an operational interconnect 审中-公开
公开(公告)号：US10671476B2
公开(公告)日：2020-06-02
申请号：US15761405
申请日：2015-09-26
申请人： Intel Corporation , Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
发明人： Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
IPC分类号： G06F11/08 , G06F13/14 , G06F11/10 , G06F11/22 , H04L1/00
摘要： There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

99. 发明申请

US20190324523A1 ALTERNATE PHYSICAL LAYER POWER MODE 审中-公开
公开(公告)号：US20190324523A1
公开(公告)日：2019-10-24
申请号：US16457930
申请日：2019-06-29
申请人： Michelle C. Jen , David J. Harriman , Zuoguo Wu , Debendra Das Sharma , Noam Dolev Geldbard
发明人： Michelle C. Jen , David J. Harriman , Zuoguo Wu , Debendra Das Sharma , Noam Dolev Geldbard
IPC分类号： G06F1/3234 , G06F1/3225 , G06F3/06
摘要： A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

100. 发明申请

US20190042380A1 CROSS-TALK GENERATION IN A MULTI-LANE LINK DURING LANE TESTING 审中-公开
公开(公告)号：US20190042380A1
公开(公告)日：2019-02-07
申请号：US15990372
申请日：2018-05-25
申请人： Debendra Das Sharma , Daniel S. Froelich
发明人： Debendra Das Sharma , Daniel S. Froelich
IPC分类号： G06F11/22 , G06F13/42
摘要： A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.

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