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91. 发明授权

US08415236B2 Methods for reducing loading effects during film formation 有权
标题翻译：降低成膜时负荷效应的方法
公开(公告)号：US08415236B2
公开(公告)日：2013-04-09
申请号：US12648309
申请日：2009-12-29
申请人： Han Guan Chew , Jinping Liu , Alex Kai Hung See , Mei Sheng Zhou
发明人： Han Guan Chew , Jinping Liu , Alex Kai Hung See , Mei Sheng Zhou
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/823412 , H01L21/823418 , H01L29/7848
摘要： A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底的第一和第二暴露部分上选择性地形成第一层。第一和第二暴露部分具有不同的尺寸并且位于第一和第二有源器件附近。在第一层形成期间，提供了包含用作形成第一层的生长组分的第一和第二源气体和用作控制第一层生长选择性的蚀刻组分的反应气体的气体混合物。反应物气体与第一和第二源气体不同，并且第一和第二源气体之一与第二暴露部分相比以较快的速率在第一暴露部分上形成第一层，而另一个源气体表现出相反的作用。

92. 发明授权

US08354347B2 Method of forming high-k dielectric stop layer for contact hole opening 有权
公开(公告)号：US08354347B2
公开(公告)日：2013-01-15
申请号：US11953881
申请日：2007-12-11
申请人： Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Chun Hui Low , Chim Seng Seet , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Chun Hui Low , Chim Seng Seet , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/461
CPC分类号： H01L21/76832 , H01L21/76895 , H01L21/76897
摘要： A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

93. 发明授权

US08293544B2 Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction 有权
标题翻译：使用热邻近校正来减少集成电路管芯内的热变化的方法和装置
公开(公告)号：US08293544B2
公开(公告)日：2012-10-23
申请号：US12220792
申请日：2008-07-28
申请人： Debora Chyiu Hyia Poon , Alex Kh See , Francis Benistant , Benjamin Colombeau , Yun Ling Tan , Mei Sheng Zhou , Liang Choo Hsia
发明人： Debora Chyiu Hyia Poon , Alex Kh See , Francis Benistant , Benjamin Colombeau , Yun Ling Tan , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/00
CPC分类号： H01L27/088 , H01L27/0211
摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
摘要翻译：制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。如果估计温度低于或高于预定目标温度（或范围），则执行TPC。可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化在退火期间。

94. 发明授权

US07960283B2 Method for reducing silicide defects in integrated circuits 有权
标题翻译：降低集成电路中硅化物缺陷的方法
公开(公告)号：US07960283B2
公开(公告)日：2011-06-14
申请号：US12825325
申请日：2010-06-28
申请人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jeff Jianhui Ye , Huang Liu , Alex K H See , Wei Lu , Hai Cong , Hui Peng Koh , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

95. 发明授权

US07879732B2 Thin film etching method and semiconductor device fabrication using same 有权
标题翻译：薄膜蚀刻方法和使用其的半导体器件制造
公开(公告)号：US07879732B2
公开(公告)日：2011-02-01
申请号：US11959034
申请日：2007-12-18
申请人： Xiang Hu , Hai Cong , Pradeep Yelehanka , Mei Sheng Zhou
发明人： Xiang Hu , Hai Cong , Pradeep Yelehanka , Mei Sheng Zhou
IPC分类号： H01L21/302 , G01R31/00 , B44C1/22
CPC分类号： H01J37/32963 , H01J37/32935
摘要： A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.
摘要翻译：一种用于蚀刻薄膜并制造半导体器件的方法包括：在监测从基板远离的端点检测层的移除的同时，对衬底上的薄膜进行蚀刻，从而通过监测薄膜蚀刻来精确控制薄膜蚀刻移除端点检测层。端点检测层形成在暴露于与要蚀刻的薄膜相同的蚀刻条件的蚀刻装置的表面上。当从蚀刻装置的表面去除预定量的端点检测层时，停止对薄膜的蚀刻。

96. 发明申请

US20090289284A1 High shrinkage stress silicon nitride (SiN) layer for NFET improvement 审中-公开
标题翻译：用于NFET改进的高收缩应力氮化硅（SiN）层
公开(公告)号：US20090289284A1
公开(公告)日：2009-11-26
申请号：US12154605
申请日：2008-05-23
申请人： Luona Goh , Jingze Tian , Wei Lu , Mei Sheng Zhou
发明人： Luona Goh , Jingze Tian , Wei Lu , Mei Sheng Zhou
IPC分类号： H01L29/78 , H01L21/3105
CPC分类号： H01L21/3125 , H01L21/0217 , H01L21/02222 , H01L21/02282 , H01L21/02348 , H01L29/6659 , H01L29/7843
摘要： A method (and semiconductor device) of forming a high shrinkage stressed silicon nitride layer for use as a contact etch stop layer (CESL) or capping layer in a stress management technique (SMT) provides increased tensile stress to a channel of an nFET device to enhance carrier mobility. A spin-on polysilazane-based dielectric material is applied to a semiconductor substrate and baked to form a film layer. The film layer is cured to remove hydrogen from the film which causes shrinkage in the film when it recrystallizes into silicon nitride. The resulting silicon nitride stressed layer introduces an increased level of tensile stress to the transistor channel region.
摘要翻译：在应力管理技术（SMT）中形成用作接触蚀刻停止层（CESL）或封盖层的高收缩应力氮化硅层的方法（和半导体器件）提供了对nFET器件的沟道增加的拉伸应力，增强载体流动性。将旋涂聚硅氮烷基介电材料施加到半导体衬底上并烘烤以形成膜层。固化膜层以从膜中除去氢，当其重结晶成氮化硅时，其导致膜的收缩。所得的氮化硅应力层向晶体管沟道区域引入增加的拉伸应力水平。

97. 发明授权

US07338909B2 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography 有权
标题翻译：用于复制半导体晶片光刻的对准标记的微蚀刻方法
公开(公告)号：US07338909B2
公开(公告)日：2008-03-04
申请号：US10872238
申请日：2004-06-18
申请人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Su , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Che Wang
发明人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Su , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Che Wang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L23/544 , H01L21/31111 , H01L21/67282 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
摘要翻译：一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

98. 发明授权

US06451706B1 Attenuation of reflecting lights by surface treatment 失效
标题翻译：表面处理反射灯衰减
公开(公告)号：US06451706B1
公开(公告)日：2002-09-17
申请号：US08657219
申请日：1996-06-03
申请人： Ron-Fu Chu , Yang Pan , Qun Ying Lin , Mei Sheng Zhou
发明人： Ron-Fu Chu , Yang Pan , Qun Ying Lin , Mei Sheng Zhou
IPC分类号： H01L21302
CPC分类号： H01L21/32137 , G03F7/091 , H01L21/0276 , H01L21/32139
摘要： A new method of avoiding resist notching in the formation of a polysilicon gate electrode in the fabrication of an integrated circuit device is described. Bare active areas are provided surrounded by field oxide isolation on a semiconductor substrate wherein the surface of the substrate has an uneven topography due to the uneven interface between the active areas and the isolation. A polysilicon layer is deposited over the active areas and the field oxide isolation of the substrate. The surface of the polysilicon layer is roughened using a plasma etching process wherein pits are formed on the surface which act as light traps. The roughened polysilicon layer is covered with a layer of photoresist. Portions of the photoresist layer are exposed to actinic light wherein reflection lights from the actinic light are trapped in the pits. The reflection lights do not reflect onto the unexposed portion of the photoresist layer. The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer wherein the absence of reflection lights reflecting onto the unexposed portion of the photoresist results in the notch-free photoresist mask in the formation of a polysilicon gate electrode in the fabrication of an integrated circuit device.
摘要翻译：描述了在集成电路器件的制造中避免形成多晶硅栅电极时的抗蚀刻缺口的新方法。在半导体衬底上围绕场氧化物隔离提供裸露的有源区域，其中由于有源区域与隔离之间的不平坦界面，衬底的表面具有不平坦的形貌。多晶硅层沉积在有源区和衬底的场氧化物隔离之上。使用等离子体蚀刻工艺将多晶硅层的表面粗糙化，其中在作为光阱的表面上形成有凹坑。粗糙多晶硅层被一层光致抗蚀剂覆盖。光致抗蚀剂层的一部分暴露于光化光，其中来自光化光的反射光被捕获在凹坑中。反射光不会反射到光致抗蚀剂层的未曝光部分上。光致抗蚀剂层被显影和图案化以形成用于多晶硅层的期望的光致抗蚀剂掩模，其中反射到光致抗蚀剂的未曝光部分上的反射光的不存在导致在制造中形成多晶硅栅电极的无切口光致抗蚀剂掩模的集成电路装置。

99. 发明授权

US06228713B1 Self-aligned floating gate for memory application using shallow trench isolation 有权
标题翻译：用于使用浅沟槽隔离的存储器应用的自对准浮动栅极
公开(公告)号：US06228713B1
公开(公告)日：2001-05-08
申请号：US09342035
申请日：1999-06-28
申请人： Yelehanka Ramachandramurthy Pradeep , Vijay Kumar Chhagan , Jie Yu , Mei Sheng Zhou
发明人： Yelehanka Ramachandramurthy Pradeep , Vijay Kumar Chhagan , Jie Yu , Mei Sheng Zhou
IPC分类号： H01H21336
CPC分类号： H01L27/11521 , H01L21/76224
摘要： A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.
摘要翻译：一种在存储器件中制作自对准浮动栅极的方法。该方法使用用于浅沟槽隔离（STI）的沟槽蚀刻对浮栅（FG）进行图案化。因为浮动栅极（FG）与凸起的STI相邻，所以在FG和CG之间消除了尖角，从而增加了栅间电介质层的有效性。该方法包括：在衬底上形成第一介质层（栅极氧化物）和多晶硅层，蚀刻通过第一电介质氧化物层和多晶硅层并进入衬底以形成沟槽。剩余的第一电介质层和多晶硅层用作隧道电介质层和浮栅。沟槽填充有隔离层。去除掩模层。在浮栅和隔离层上形成隔间电介质层和控制栅极。

100. 发明授权

US6156598A Method for forming a lightly doped source and drain structure using an L-shaped spacer 有权
标题翻译：使用L形间隔物形成轻掺杂源极和漏极结构的方法
公开(公告)号：US6156598A
公开(公告)日：2000-12-05
申请号：US460113
申请日：1999-12-13
申请人： Mei Sheng Zhou , Yelehanka Ramachandramurthy Pradeep , Jie Yu , Ying Keung Leung
发明人： Mei Sheng Zhou , Yelehanka Ramachandramurthy Pradeep , Jie Yu , Ying Keung Leung
IPC分类号： H01L21/265 , H01L21/311 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/66598 , H01L21/2652 , H01L21/31144 , H01L21/823814 , H01L21/823864 , H01L29/6659
摘要： A method for forming an L-shaped spacer using a sacrificial organic top coating, then using the L-shaped spacer to simultaneously implant lightly doped source and drain extensions through the L-shaped spacer while implanting source and drain regions beyond the L-shaped spacer. A semiconductor structure is provided having a gate structure thereon. A liner oxide layer is formed on the gate structure. A dielectric spacer layer is formed on the liner oxide layer. In the preferred embodiments, the dielectric spacer layer comprises a silicon nitride layer or a silicon oxynitride layer. A sacrificial organic layer is formed on the dielectric spacer layer. The sacrificial organic layer and the dielectric spacer layer are anisotropically etched to form spacers comprising a triangle-shaped sacrificial organic structure and an L-shaped dielectric spacer. The triangle-shaped sacrificial organic structure is removed leaving an L-shaped dielectric spacer. Impurity ions are implanted into the surface of the semiconductor structure forming lightly doped source and drain extensions where the ions are implanted through the L-shaped spacer, and forming source and drain regions beyond the L-shaped spacer where the ions are implanted without passing through the L-shaped spacer.
摘要翻译：使用牺牲有机顶涂层形成L形间隔物的方法，然后使用L形间隔物同时将轻掺杂的源极和漏极延伸部注入L型间隔物，同时将源极和漏极区域注入超过L形间隔物。提供其上具有栅极结构的半导体结构。在栅极结构上形成衬里氧化物层。介电间隔层形成在衬垫氧化物层上。在优选实施例中，电介质间隔层包括氮化硅层或氮氧化硅层。在电介质间隔层上形成牺牲有机层。牺牲有机层和电介质间隔层被各向异性蚀刻以形成包括三角形牺牲有机结构和L形介电间隔物的间隔物。去除三角形牺牲有机结构留下L形介电隔离物。将杂质离子注入到形成轻掺杂源极和漏极延伸部分的半导体结构的表面中，其中离子通过L形间隔物注入，并且形成超过L形间隔物的源极和漏极区域，其中离子被注入而不通过 L形间隔物。

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