专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07977750B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07977750B2
公开(公告)日：2011-07-12
申请号：US12636375
申请日：2009-12-11
申请人： Hidehito Kitakado , Ritsuko Kawasaki , Kenji Kasahara
发明人： Hidehito Kitakado , Ritsuko Kawasaki , Kenji Kasahara
IPC分类号： H01L21/00
CPC分类号： H01L29/66765 , G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78627 , H01L29/78633
摘要： The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.
摘要翻译：本发明提供了一种半导体器件，其中布置在每个电路中的底栅TFT或反向交错TFT适当地构成为与各个电路的功能一致，从而提高了半导体器件的工作效率和可靠性。在该结构中，像素TFT中的LDD区域布置成不与沟道保护绝缘膜重叠，并且通过其至少一部分与栅电极重叠。驱动电路的N沟道TFT中的LDD区域布置成不与沟道保护绝缘膜重叠，并且通过其至少一部分与栅电极重叠。驱动电路的P沟道TFT中的LDD区域布置成与沟道保护绝缘膜重叠并与栅电极重叠。

92. 发明申请

US20080003729A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080003729A1
公开(公告)日：2008-01-03
申请号：US11896155
申请日：2007-08-30
申请人： Hideto Ohnuma , Masayuki Sakakura , Yasuhiro Mitani , Takuya Matsuo , Hidehito Kitakado
发明人： Hideto Ohnuma , Masayuki Sakakura , Yasuhiro Mitani , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/84
CPC分类号： H01L29/66757 , H01L21/02532 , H01L21/02667 , H01L21/02672 , H01L21/02686 , H01L27/12 , H01L27/1277
摘要： A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.
摘要翻译：具有抑制空腔制造的结晶半导体膜的半导体器件及其制造方法本发明的半导体器件的制造方法包括以下步骤：在具有绝缘表面的基板上形成非晶硅膜，添加金属元素如Ni，用于促进结晶到非晶硅膜，进行热处理以使非晶硅膜结晶，从而在基板上形成晶体硅膜，去除在晶体硅膜表面形成的氧化硅膜，通过含有有机溶剂和氟化物的溶液进行热处理，并向结晶硅膜照射激光或强光。

93. 发明授权

US09240491B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09240491B2
公开(公告)日：2016-01-19
申请号：US14130844
申请日：2012-06-26
申请人： Kazuatsu Ito , Hidehito Kitakado
发明人： Kazuatsu Ito , Hidehito Kitakado
IPC分类号： H01L29/10 , H01L29/66 , H01L27/12 , H01L29/786
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/66969 , H01L29/78618 , H01L29/78645 , H01L29/78696
摘要： A semiconductor device (100A) has an oxide semiconductor layer (11). The oxide semiconductor layer (11) has a channel region (11c), and a source region (11s) and drain region (11d) positioned on respective sides of the channel region (11c). The source region (11s) has a low-resistance source region (11sx) that has a lower resistance than the channel region (11c), and the drain region (11d) has a low-resistance drain region (11dx) that has a lower resistance than the channel region (11c). The carrier concentrations of the low-resistance source region (11sx) and the low-resistance drain region (11dx) become progressively lower from a connecting portion between a source electrode (17) and the low-resistance source region (11sx) and a connecting portion between a drain electrode (18) and the low-resistance drain region (11dx) towards the channel region (11c).
摘要翻译：半导体器件（100A）具有氧化物半导体层（11）。氧化物半导体层（11）具有沟道区域（11c）以及位于沟道区域（11c）的相应侧面上的源极区域（11s）和漏极区域（11d）。源极区域（11s）具有比沟道区域（11c）低的电阻的低电阻源极区域（11sx），漏极区域（11d）具有低电阻漏极区域（11dx）电阻比通道区域（11c）。低电阻源极区域（11sx）和低电阻漏极区域（11dx）的载流子浓度从源电极（17）和低电阻源极区域（11sx）之间的连接部分逐渐降低，并且连接漏极电极（18）和低电阻漏极区域（11dx）之间的部分朝向沟道区域（11c）。

94. 发明授权

US08421944B2 Display device substrate, display device, and wiring substrate 有权
标题翻译：显示装置用基板，显示装置以及配线基板
公开(公告)号：US08421944B2
公开(公告)日：2013-04-16
申请号：US12530557
申请日：2007-12-19
申请人： Hidehito Kitakado
发明人： Hidehito Kitakado
IPC分类号： G02F1/136 , H01L31/112
CPC分类号： G02F1/136286 , G02F1/136213 , H01L27/124 , H01L27/3276 , H01L29/78645
摘要： The present invention provides a display device substrate, a display device, and a wiring substrate, each permitting more flexible wiring design and a reduction in area of wirings with suppressing wiring defects.The present invention is a display device substrate including, on a main surface of a substrate, a structure of alternating layers of: a plurality of interlayer insulating films; and three or more wiring layers, wherein the display device substrate includes a data wiring, and the data wiring is positioned in a third or higher wiring layer from a side of the substrate.
摘要翻译：本发明提供了一种显示装置基板，显示装置和布线基板，每个都允许更灵活的布线设计和布线面积的减小，同时抑制布线缺陷。本发明是一种显示装置基板，在基板的主表面上具有交替层的结构：多个层间绝缘膜; 以及三个以上的布线层，其中，所述显示装置用基板包括数据布线，所述数据布线位于从所述基板侧的第三以上布线层。

95. 发明申请

US20120256184A1 SEMICONDUCTOR DEVICE, ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE 有权
标题翻译：半导体器件，有源矩阵衬底和显示器件
公开(公告)号：US20120256184A1
公开(公告)日：2012-10-11
申请号：US13515921
申请日：2010-11-02
申请人： Seiji Kaneko , Hidehito Kitakado
发明人： Seiji Kaneko , Hidehito Kitakado
IPC分类号： H01L29/786
CPC分类号： H01L29/78633 , G02F1/1368 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： A switching element (a semiconductor device) (18) having a top gate electrode (21) and a bottom gate electrode (23) is provided with a silicon layer (a semiconductor layer) (SL) that is arranged between the top gate electrode (21) and the bottom gate electrode (a light-shielding film) (23) and that has a source region (24), a drain region (28), a channel region (26), and low-concentration impurity regions (25, 27). Furthermore, the bottom gate electrode (23) is arranged so as to overlap the channel region (26), a part of the low-concentration impurity region (25), which is adjacent to the source region (24), and a part of the low-concentration impurity region (27), which is adjacent to the drain region (18). The bottom gate electrode (23) is controlled so as to have a prescribed potential.
摘要翻译：具有顶栅极（21）和底栅电极（23）的开关元件（半导体器件）（18）设置有硅层（半导体层）（SL），其设置在顶栅电极 21）和底栅极（遮光膜）（23），并且具有源极区（24），漏极区（28），沟道区（26）和低浓度杂质区（25， 27）。此外，底栅电极（23）被布置成与沟道区（26）重叠，与源区（24）相邻的低浓度杂质区（25）的一部分，和与漏极区（18）相邻的低浓度杂质区（27）。底栅极（23）被控制为具有规定的电位。

96. 发明申请

US20120146038A1 SEMICONDUCTOR DEVICE, ACTIVE MATRIX SUBSTRATE, AND DISPLAY DEVICE 审中-公开
标题翻译：半导体器件，有源矩阵衬底和显示器件
公开(公告)号：US20120146038A1
公开(公告)日：2012-06-14
申请号：US13392273
申请日：2010-08-26
申请人： Hidehito Kitakado
发明人： Hidehito Kitakado
IPC分类号： H01L29/786
CPC分类号： H01L27/1214 , G02F1/13454 , G02F2001/13312 , H01L29/78624 , H01L29/78633 , H01L29/78645 , H01L29/78648
摘要： Provided are a semiconductor device that can achieve leakage current reduction irrespective of an ambient temperature, an active matrix substrate in which such a semiconductor device is used, and a display device. In a switching portion (semiconductor device) (18) including a plurality of thin film transistors connected in series, there are provided a plurality of gate electrodes (g1 to g4); channel regions (30) and low-concentration impurity-doped regions (29) that are included in a silicon layer (semiconductor layer) (SL) provided below the plurality of gate electrodes (g1 to g4), and are provided in the plurality of thin film transistors, respectively; and a bottom gate electrode (21) provided below the silicon layer (SL). To the bottom gate electrode (29), a signal in the same phase as that of a signal for the gate electrodes (g1 to g4) is supplied.
摘要翻译：提供了能够实现与环境温度无关的漏电流降低的半导体器件，使用这种半导体器件的有源矩阵基板和显示装置。在包括串联连接的多个薄膜晶体管的开关部（半导体器件）（18）中，设置有多个栅电极（g1〜g4）。包含在设置在多个栅电极（g1〜g4）的下方的硅层（半导体层）（SL）中的多个沟道区域（30）和低浓度杂质掺杂区域（29）薄膜晶体管; 以及设置在硅层（SL）下方的底栅电极（21）。向底栅电极（29）提供与栅电极（g1〜g4）的信号相同相位的信号。

97. 发明授权

US07868398B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07868398B2
公开(公告)日：2011-01-11
申请号：US11542217
申请日：2006-10-04
申请人： Takeshi Noda , Hidehito Kitakado , Takuya Matsuo
发明人： Takeshi Noda , Hidehito Kitakado , Takuya Matsuo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66757 , H01L29/42384 , H01L29/78603 , H01L29/78621 , H01L29/78675
摘要： A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, and LDD regions are formed in the semiconductor layer. A main gate is formed on the gate insulating film. A sub-gate is formed on the main gate and the gate insulating film so as to cover a part of the main gate and either the LDD regions adjacent to the source region or the drain region. An interlayer insulating film containing hydrogen is formed on the sub-gate, main gate, and gate insulating film. Subsequently, a heat treatment for hydrogenation is performed to terminate a crystal defect of the semiconductor layer with hydrogen.
摘要翻译：提供了可以提高在使用GOLD结构的情况下氢化处理的效果的半导体器件及其制造方法。在半导体层上形成栅极绝缘膜，在半导体层中形成源极区，漏极区，LDD区。在栅极绝缘膜上形成主栅极。在主栅极和栅极绝缘膜上形成子栅极，以覆盖主栅极的一部分和与源极区域或漏极区域相邻的LDD区域。在子栅极，主栅极和栅极绝缘膜上形成含有氢的层间绝缘膜。随后，进行用于氢化的热处理，以氢终止半导体层的晶体缺陷。

98. 发明授权

US07638846B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07638846B2
公开(公告)日：2009-12-29
申请号：US11703667
申请日：2007-02-08
申请人： Hidehito Kitakado , Ritsuko Kawasaki , Kenji Kasahara
发明人： Hidehito Kitakado , Ritsuko Kawasaki , Kenji Kasahara
IPC分类号： H01L21/00
CPC分类号： H01L29/66765 , G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78627 , H01L29/78633
摘要： The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted, stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.
摘要翻译：本发明提供了一种半导体器件，其中布置在每个电路中的底栅TFT或倒置的交错TFT适当地构造成与各个电路的功能一致，从而提高半导体的操作效率和可靠性设备。在该结构中，像素TFT中的LDD区域布置成不与沟道保护绝缘膜重叠，并且通过其至少一部分与栅电极重叠。驱动电路的N沟道TFT中的LDD区域布置成不与沟道保护绝缘膜重叠，并且通过其至少一部分与栅电极重叠。驱动电路的P沟道TFT中的LDD区域布置成与沟道保护绝缘膜重叠并与栅电极重叠。

99. 发明授权

US07625785B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07625785B2
公开(公告)日：2009-12-01
申请号：US11896155
申请日：2007-08-30
申请人： Hideto Ohnuma , Masayuki Sakakura , Yasuhiro Mitani , Takuya Matsuo , Hidehito Kitakado
发明人： Hideto Ohnuma , Masayuki Sakakura , Yasuhiro Mitani , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/84
CPC分类号： H01L29/66757 , H01L21/02532 , H01L21/02667 , H01L21/02672 , H01L21/02686 , H01L27/12 , H01L27/1277
摘要： A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.
摘要翻译：具有抑制空腔制造的结晶半导体膜的半导体器件及其制造方法本发明的半导体器件的制造方法包括以下步骤：在具有绝缘表面的基板上形成非晶硅膜，添加金属元素如Ni，用于促进结晶到非晶硅膜，进行热处理以使非晶硅膜结晶，从而在基板上形成晶体硅膜，去除在晶体硅膜表面形成的氧化硅膜，通过含有有机溶剂和氟化物的溶液进行热处理，并向结晶硅膜照射激光或强光。

100. 发明授权

US07528410B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07528410B2
公开(公告)日：2009-05-05
申请号：US11584524
申请日：2006-10-23
申请人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
发明人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
IPC分类号： H01L29/12 , H01L29/786
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1259 , H01L29/6675 , H01L29/78621 , H01L29/78648
摘要： A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: forming a semiconductor layer 3 having a source and a drain regions 10, 11, and LDD regions 16, 17; a gate insulating film 5; and a gate electrode 6; forming a first and a second interlayer insulating films 24, 25 over the gate electrode 6 and the gate insulating film 5; forming contact holes 25a, 25c to these interlayer insulating films so as to be located over each of the source region and the drain region; and an opening portion 25b to these interlayer insulating films so as to be located over the gate electrode and the LDD region; forming a second gate electrode 26b by a conductive film in the opening portion so as to cover the gate electrode and the LDD region; and a pixel electrode 26a over the second interlayer insulating film; removing the gate insulating film in the contact hole; and forming wirings 27, 28 connected to each the source region and the drain region.
摘要翻译：公开了可以通过减少掩模数而降低成本的半导体器件，并且公开了一种用于制造半导体器件的方法。制造半导体器件的方法包括以下步骤：形成具有源极和漏极区域10,11以及LDD区域16,17的半导体层3; 栅极绝缘膜5; 和栅电极6; 在栅极电极6和栅极绝缘膜5上形成第一和第二层间绝缘膜24,25; 将这些层间绝缘膜形成接触孔25a，25c，以便位于源极区域和漏极区域的每一个上; 和这些层间绝缘膜的开口部25b，以位于栅电极和LDD区之上; 通过开口部中的导电膜形成第二栅电极26b，以覆盖栅电极和LDD区; 和在第二层间绝缘膜上方的像素电极26a; 去除接触孔中的栅极绝缘膜; 以及形成连接到每个源极区域和漏极区域的布线27,28。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式