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91. 发明申请

US20050055487A1 Rotating docking station 审中-公开
标题翻译：旋转坞站
公开(公告)号：US20050055487A1
公开(公告)日：2005-03-10
申请号：US10654812
申请日：2003-09-04
申请人： Toshiyuki Tanaka , Hiroshi Nakamura , Martin Riddiford
发明人： Toshiyuki Tanaka , Hiroshi Nakamura , Martin Riddiford
IPC分类号： H05K5/02 , G06F1/16 , G06F13/00
CPC分类号： G06F1/1632
摘要： A docking station useful for connecting a portable computing device to a network or other external device. The docking station includes a first supporting device having a first mounting surface and connector thereon to support and electrically connect to a portable computing device. The first mounting surface is rotationally mounted to a base, and slightly inclined with respect to the underside of the base. Such configuration allows the portable computing device to lie substantially horizontal and to be rotated about a substantially vertical axis. The docking station further includes a second supporting device having a second mounting surface to support the first supporting device thereon. The second mounting surface is mounted on a base, and is significantly inclined with respect to its base. Such configuration allows the portable computing device to lie substantially vertical and to be rotated about a substantially horizontal axis.
摘要翻译：用于将便携式计算设备连接到网络或其他外部设备的坞站。对接站包括第一支撑装置，其具有第一安装表面和连接器，以支撑并电连接到便携式计算装置。第一安装表面旋转地安装到基座上，并相对于底座的下侧略微倾斜。这种配置允许便携式计算设备基本上水平地并且围绕基本垂直的轴线旋转。对接站还包括具有第二安装表面以在其上支撑第一支撑装置的第二支撑装置。第二安装表面安装在基座上，并且相对于其底部显着倾斜。这种配置允许便携式计算设备基本上垂直并且围绕基本上水平的轴线旋转。

92. 发明申请

US20050052833A1 Interlocking mechanism for a display 失效
标题翻译：显示器的联锁机制
公开(公告)号：US20050052833A1
公开(公告)日：2005-03-10
申请号：US10654787
申请日：2003-09-04
申请人： Toshiyuki Tanaka , Hiroshi Nakamura , Martin Riddiford
发明人： Toshiyuki Tanaka , Hiroshi Nakamura , Martin Riddiford
IPC分类号： H05K5/02 , G06F1/16 , H05K5/03
CPC分类号： G06F1/1643 , G06F1/162 , G06F1/1679 , G06F1/1681 , G06F1/1683 , G06F1/1688 , G06F1/169
摘要： One aspect of an embodiment of the invention provides an apparatus for interlocking a display housing to a display support member. The apparatus comprises a lever, a first fastener and a second fastener. The first fastener is pivotally coupled to one end of the lever. The second fastener, however, is coupled to the other end of the lever. The second fastener engages a display support member when the lever is placed in a first state and disengages from the display support member when the lever is placed in a second state. The adjustment of the lever to move from a first state to a second state is in response to an event performed on the first fastener.
摘要翻译：本发明的实施例的一个方面提供了一种用于将显示器外壳与显示器支撑构件互锁的装置。该装置包括杆，第一紧固件和第二紧固件。第一紧固件枢转地连接到杠杆的一端。然而，第二紧固件联接到杠杆的另一端。当杠杆处于第一状态时，第二紧固件与显示器支撑构件接合，并且当杆处于第二状态时，第二紧固件与显示器支撑构件脱离接合。杠杆从第一状态移动到第二状态的调节是响应于在第一紧固件上执行的事件。

93. 发明授权

US06847524B2 Electronic apparatus having cooling unit for cooling heat-generating component 有权
标题翻译：具有用于冷却发热部件的冷却单元的电子设备
公开(公告)号：US06847524B2
公开(公告)日：2005-01-25
申请号：US10164017
申请日：2002-06-07
申请人： Kentaro Tomioka , Hiroshi Nakamura
发明人： Kentaro Tomioka , Hiroshi Nakamura
IPC分类号： G06F1/20 , H05K7/20
CPC分类号： H05K7/20154 , G06F1/203
摘要： An electronic apparatus comprises a housing containing a heat-generating component, and a cooling unit. The cooling unit includes a heat sink thermally connected to the heat-generating component, a first air passage for guiding air outside the housing to the heat sink and guiding air heated by heat exchange with the heat sink to the outside of the housing, and a second air passage for guiding air within the housing to the outside of the housing.
摘要翻译：电子设备包括容纳发热部件的壳体和冷却单元。冷却单元包括热连接到发热部件的散热器，用于将壳体外部的空气引导到散热器并将通过与散热器的热交换加热的空气引导到壳体外部的第一空气通道，以及第二空气通道，用于将壳体内的空气引导到壳体的外部。

94. 发明授权

US06836444B2 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield 有权
标题翻译：半导体存储器件能够实现具有高操作可靠性和高产量的芯片
公开(公告)号：US06836444B2
公开(公告)日：2004-12-28
申请号：US10452128
申请日：2003-06-03
申请人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
发明人： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC分类号： G11C1100
CPC分类号： G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes a memory cell array comprising memory cell units arranged in an array form, first blocks including first memory cell units each having at least one memory cell and at least one selection gate transistor, and second blocks including second memory cell units each having at least one memory cell and at least one selection gate transistor, wherein the first blocks are arranged on both end portions of the memory cell array, the second blocks are arranged in another portion, and a structure of the first memory cell units on the end portions of the memory cell array is different from a structure of the second memory cell units.
摘要翻译：半导体存储器件包括存储单元阵列，其包括以阵列形式布置的存储单元单元，第一块包括每个具有至少一个存储单元和至少一个选择栅极晶体管的第一存储单元单元，以及包括第二存储单元单元的第二块具有至少一个存储单元和至少一个选择栅晶体管，其中所述第一块布置在所述存储单元阵列的两端部分上，所述第二块布置在另一部分中，并且所述第一存储单元单元的结构存储单元阵列的端部与第二存储单元单元的结构不同。

95. 发明授权

US06833606B2 Fabrication of a heterojunction bipolar transistor with integrated MIM capacitor 失效
标题翻译：具有集成MIM电容器的异质结双极晶体管的制造
公开(公告)号：US06833606B2
公开(公告)日：2004-12-21
申请号：US10289684
申请日：2002-11-07
申请人： Hiroshi Nakamura , Ting Cheong Ang , Kian Siong Ang , Subrata Halder , Geok Ing Ng
发明人： Hiroshi Nakamura , Ting Cheong Ang , Kian Siong Ang , Subrata Halder , Geok Ing Ng
IPC分类号： H01L2706
CPC分类号： H01L27/0605 , H01L21/8252
摘要： In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.
摘要翻译：在本发明中，形成半导体器件，其包括位于异质结构的上表面上的MIM电容器，从其定义附近HBT的发射极，基极和集电极部分。以这种方式，电容器和HBT分别具有基本上共同的结构，HBT的基极和发射极电极分别由与上部和下部电容器板相同的金属层制成。此外，由于在定义HBT结构之前形成电容器的绝缘体区域，所以使用的电介质材料可以通过等离子体增强工艺沉积，而不会损坏HBT结构。

96. 发明授权

US06809365B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US06809365B2
公开(公告)日：2004-10-26
申请号：US10212060
申请日：2002-08-06
申请人： Hiroshi Nakamura , Kenichi Imamiya
发明人： Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , G11C11/5621 , G11C16/0483 , G11C16/26 , H01L27/115 , H01L27/11529 , H01L2924/0002 , H01L2924/00
摘要： In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.
摘要翻译：在由多个存储单元串联连接的NAND单元组成的EEPROM中，通过数据读取操作选择的块中的存储单元的控制栅极电压Vread与电压Vsg1，Vsg2 在所选择的块中选择晶体管的选择栅极，从而使得可以实现高速读取，而不会导致插入在选择栅极和选择晶体管的沟道之间的绝缘膜的击穿。如果使存储器单元的控制栅极电压与选择的电压不同，则也可以在DINOR单元，AND单元，NOR单元和与其连接的单个存储单元的NAND单元中实现高速读数。选择晶体管的栅极。

97. 发明授权

US06808846B2 Negative electrode for lithium secondary battery and manufacturing method thereof 有权
标题翻译：锂二次电池用负极及其制造方法
公开(公告)号：US06808846B2
公开(公告)日：2004-10-26
申请号：US10046697
申请日：2002-01-17
申请人： Takuya Hashimoto , Atsushi Fukui , Hiroshi Nakamura , Shin Fujitani
发明人： Takuya Hashimoto , Atsushi Fukui , Hiroshi Nakamura , Shin Fujitani
IPC分类号： H01M462
CPC分类号： H01M4/0471 , B22F2009/041 , B22F2998/00 , B22F2999/00 , C22C1/0416 , C22C21/00 , C22C45/08 , C22C2200/02 , H01M4/0483 , H01M4/13 , H01M4/38 , H01M4/386 , H01M4/40 , H01M4/624 , H01M4/626 , H01M4/661 , H01M10/052 , H01M2004/021 , B22F9/04 , B22F3/22 , B22F3/10 , B22F2201/11
摘要： A negative electrode for lithium secondary battery characterized in that the electrode is obtained by sintering a mixture of an active material alloy and a binder disposed on a current collector, or a mixture of an active material alloy, conductive metal powder and a binder disposed on a current collector, and the active material alloy after sintered is substantially amorphous.
摘要翻译：一种锂二次电池用负极，其特征在于，通过烧结活性物质合金和设置在集电体上的粘合剂的混合物，或者将活性物质合金，导电性金属粉末和粘合剂的混合物烧结而获得的电极集电体，烧结后的活性物质合金基本上是无定形的。

98. 发明授权

US06791499B2 Electronic apparatus and antenna installation method 失效
标题翻译：电子仪器和天线安装方法
公开(公告)号：US06791499B2
公开(公告)日：2004-09-14
申请号：US10310846
申请日：2002-12-06
申请人： Hiroshi Nakamura , Hiroyuki Minaguchi , Toshiyuki Hirota
发明人： Hiroshi Nakamura , Hiroyuki Minaguchi , Toshiyuki Hirota
IPC分类号： H01Q124
CPC分类号： H01Q1/2266 , G06F1/1616 , G06F1/1656 , G06F1/1698 , H01Q1/22
摘要： Antenna elements for a wireless unit provided in a housing body are sandwiched between a housing base and a housing cover. The size and thickness of the apparatus housing are thus reduced, and the structure of installing the antenna elements is simplified into an economically advantageous structure. The antenna elements are provided, with the surfaces of their antenna patterns all exposed from the side walls of the housing body. It is hence possible to realize an antenna unit with stable and high performance without being electromagnetically influenced by components installed in the housing.
摘要翻译：设置在壳体中的用于无线单元的天线元件被夹在壳体基座和壳体盖之间。因此，装置壳体的尺寸和厚度减小，并且将天线元件的安装结构简化为经济上有利的结构。提供天线元件，其天线图案的表面全部从壳体的侧壁露出。因此，可以实现具有稳定且高性能的天线单元，而不会受到安装在壳体中的部件的电磁影响。

99. 发明授权

US06781776B2 Magnetic card reader and magnetic data reproduction method using signal peak point intervals 有权
标题翻译：磁卡阅读器和使用信号峰值间隔的磁数据再现方法
公开(公告)号：US06781776B2
公开(公告)日：2004-08-24
申请号：US10358254
申请日：2003-02-05
申请人： Mitsuo Yokozawa , Hiroshi Nakamura , Shinya Morozumi , Keiji Hoson
发明人： Mitsuo Yokozawa , Hiroshi Nakamura , Shinya Morozumi , Keiji Hoson
IPC分类号： G11B2504
CPC分类号： G11B5/00808 , G06K7/084 , G11B5/008 , G11B5/02 , G11B5/09 , G11B20/00007 , G11B20/10009 , G11B20/10203 , G11B20/10314 , G11B20/14 , G11B2020/1062
摘要： A magnetic card reader for causing a magnetic card to make a move relative to a magnetic head and reproducing data on the magnetic card by the magnetic head, said magnetic card reader includes an amplifier for amplifying a magnetic signal provided by the magnetic head, a peak detection section for detecting a peak point of amplifier output from the amplifier output, a data reproduction section for reproducing digital data based on the interval between the peak points, an anomaly detection section for detecting an anomaly of the peak point interval and an output value storage section for converting the amplifier output from analog form into digital form every predetermined time and storing the provided data.
摘要翻译：一种用于使磁卡相对于磁头移动并由磁头再现磁卡上的数据的磁卡阅读器，所述磁卡阅读器包括用于放大由磁头提供的磁信号的放大器，用于检测来自放大器输出的放大器输出的峰值点的检测部分，用于基于峰值点之间的间隔再现数字数据的数据再现部分，用于检测峰值点间隔的异常的异常检测部分和输出值存储用于将每个预定时间的模拟形式的放大器输出转换为数字形式并存储所提供的数据。

100. 发明授权

US06717858B2 Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays 有权
公开(公告)号：US06717858B2
公开(公告)日：2004-04-06
申请号：US10190069
申请日：2002-07-03
申请人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
发明人： Koichi Kawai , Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
IPC分类号： G11C1606
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/3454
摘要： A plurality of memory cell arrays are provided. Each of the memory cell arrays has a plurality of memory cells and the memory cells are connected to a plurality of word lines. Corresponding with the plurality of memory cell arrays, a plurality of word line drive circuits and a plurality of bit line control circuits are provided. Each of the word line drive circuits selects and drives the word lines of the corresponding memory cell array. Each of the bit control circuits carries out verifying reading for the data written in advance in the plurality of memory cells of the corresponding memory cell array, and controls a select and driving operation for the word lines of the corresponding word line drive circuit based on a result of the verifying reading.

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