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    • 92. 发明授权
    • Semiconductor memory including means for noise suppression
    • 半导体存储器包括用于噪声抑制的装置
    • US4943949A
    • 1990-07-24
    • US802197
    • 1985-11-25
    • Yasunori YamaguchiKanji OishiKazuyuki Miyazawa
    • Yasunori YamaguchiKanji OishiKazuyuki Miyazawa
    • G11C11/401G11C11/4096
    • G11C11/4096
    • A half precharge type dynamic RAM has a pair of data lines to which a plurality of dynamic memory cells are coupled. The paired data lines are set in advance before a read operation at a reference potential which is equal to one half of the supply voltage. One of the paired data lines is switched to have a higher or lower level than the reference potential by the memory cell selected. The potential difference applied between the paired data lines is amplified by the operation of a sense amplifier. Here, an address selecting MOSFET in the memory cell has a gate capacitance which will undesirably couple a word line and the data lines. As a result, one of the data lines has its level changed in an undesired manner. The noise inparted between the paired data lines by such coupling noise components can be substantially neglected by adopting a dummy MOSFET which operates to impart coupling noise components corresponding to the noise components caused by the address selecting MOSFET gate capacitance.
    • 半预充电型动态RAM具有耦合多个动态存储单元的一对数据线。 在等于电源电压的一半的参考电位的读取操作之前,预先设置成对的数据线。 成对数据线中的一个被选择的存储器单元切换到比参考电位更高或更低的电平。 通过读出放大器的操作来放大配对数据线之间的电位差。 这里,存储单元中的地址选择MOSFET具有将不期望地耦合字线和数据线的栅极电容。 结果,其中一条数据线的水平以不期望的方式改变。 通过这样的耦合噪声分量在成对数据线之间插入的噪声可以通过采用虚拟MOSFET来实质上被忽略,该虚拟MOSFET用于赋予与由地址选择MOSFET栅极电容引起的噪声分量相对应的耦合噪声分量。